Yeah, unfortunately you're right. An LME49710 + LME49600 will do this job just fine and take up less space, but it's just not fun or a challenge.
I quite like this, but the FET output stage is a bit idiosyncratic for my liking. You could use a FET source follower with a BIP current source load for true class A output? No need to skimp on the supply current - this is DIY.
Would you elaborate ?
It would seem to me N to P would be more important
than N to N and/or P to P ?
Not enough. Thermal dependence of current of 1'st stage (diff-pair + current source in the tail) is amplified by the 2'nd stage, and thermal dependence of it's current _added_ to it.
I think I'd start with this one, with updated JFETs. The output stage can use a J202 (maybe with a 2n5461 as the p-ch compliment), perhaps with cascoded drains to increase the rail voltage capability, a la Burson HD/OPA-Earth.
The input stage can be bipolar (2sc1845, etc.) or cascoded 2sk170. Also worth looking at is the Toshiba 2sk241 small-signal depletion-mode MOSFET for the input stage - low Vdsmax makes a cascode mandatory.
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John,
Would you care to comment on the topology in post#306 ?
Please ignore the devices. They are of course not up to date.
Some specific questions :
1. Is the current mirror of the first stage really necessary ?
Could we not just tape the drive voltage to the 2nd stage off the resistors (if necessary different values) ?
2. Cascode vs no cascode for 2nd stage ?
Are the cascode there for open loop frequency response reasons ?
Thanks,
Patrick
Would you care to comment on the topology in post#306 ?
Please ignore the devices. They are of course not up to date.
Some specific questions :
1. Is the current mirror of the first stage really necessary ?
Could we not just tape the drive voltage to the 2nd stage off the resistors (if necessary different values) ?
2. Cascode vs no cascode for 2nd stage ?
Are the cascode there for open loop frequency response reasons ?
Thanks,
Patrick
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At wafer probe, the probe setup can be used to test adjacent die, and they can setup the inker to either mark the good pairs, or mark those which do not meet requirements. Subsequent auto pick and place can easily visually detect either lack of an ink dot, or a specific color.
After test, the wafer is first bonded to a sticky plastic film, the either scribed and broked like Scott mentions, or the wafer is sawcut between the die to the film as I've been involved with. The "expanded" I mentioned is a film which can be stretched, and a rounded probe under the die can push up so that the film releases the die to the vacuum pick.
My work back in the day was with mil spec hybrids, so laser scribing was a definite no-no...we had to pass PIND testing.
jn
A wafer backside is generally the collector for power zistors, and drain for power fets.
Small signal devices can be isolated from backside by a reverse biased pn junction, or even a grown isolation like silicon nitride.
My work with individual or dual transistors/fets had only the one layer of aluminum in a 2-d pattern.. MSI and LSI of course had multiple layers with crossovers. Copper traces weren't around in my day, we had to fight the raptors..
John
Yeah, about 13pF put across the feedback resistor brings the spike down to about 6dB (from 15 or so). Distortion is slightly worse though. Someone else needs to step up and start modeling. Too much yapping about dies and other things and not enough modeling!