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Old 16th September 2012, 04:14 PM   #971
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Well, I don't know what I mean, Richard, except that to remove active parts from my example schematic would compromise it, somewhat. However, many here would add 10 more active devices in the follower stage, etc. I do shake my head at that.
By the way, this design would not need a servo if the gain were reduced to headphone levels, if that bothers you. '-) Just use a monolithic dual fet at the input.
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Old 16th September 2012, 05:22 PM   #972
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I combined Scott's cascoded gain stage with my CCB, and it sims Ok. I kludged in a pair of PNPs instead of P-JFETs in the LTP, and it doesn't appear to hurt.
THD20 sims at -95 dBr at 4V into 600R, without much optimization. GBW is 25 MHz, small-signal.
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Old 16th September 2012, 06:59 PM   #973
RNMarsh is offline RNMarsh  United States
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I combined Scott's cascoded gain stage with my CCB, and it sims Ok. I kludged in a pair of PNPs instead of P-JFETs in the LTP, and it doesn't appear to hurt.
THD20 sims at -95 dBr at 4V into 600R, without much optimization. GBW is 25 MHz, small-signal.
Curious... open loop BW and gain is ______ ?
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Old 16th September 2012, 08:22 PM   #974
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Curious... open loop BW and gain is ______ ?
You can resistively load the high gain node to ground to give you any OLBW you want (within reason). I admit it is a sideshow but this circuit makes it easy to explore the issue, (no R ) Aol = ~120dB and BW = 50Hz and does it matter if you reduce it to 66dB and 20kHz?
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Old 16th September 2012, 08:27 PM   #975
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I found it interesting that George Wilson presented an all NPN and NJFET op-amp in >>1968<< that had 200V/usec slew rate and 50MHz BW. This WAS potentially good for audio but I never saw any followup.

Yup, the same Wilson as in the current mirror.
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Old 16th September 2012, 08:30 PM   #976
coluke is offline coluke  Italy
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Did match a few JFETs, and put them in the circuit in #945 - interestingly enough, got overall better DC balance and drift as expected, but THD raised quite bit: still < 0.001% @ 0dBV, 1 kHz into 30 ohm, with 2nd accounting for most of the raise. Seems that the best operating point as far as the DC balance is concerned is not the point of best AC symmetry (unless the very low figures I got a few days ago were due to some lucky cancellation effects...). Sounds anyway a little bit strange: what am I missing?

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Old 16th September 2012, 08:39 PM   #977
coluke is offline coluke  Italy
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You can resistively load the high gain node to ground to give you any OLBW you want (within reason). I admit it is a sideshow but this circuit makes it easy to explore the issue, (no R ) Aol = ~120dB and BW = 50Hz and does it matter if you reduce it to 66dB and 20kHz?
A trick I used when playing with discrete CFA, but it seems a purely cosmetic effect, isn't it? Once OLG @ 20 kHz is fixed, I think there's no point in deliberately lowering it at LF just to get a flat OLBW - 120 dB @50 Hz and 70 dB @ 20 kHz is better than 70 dB from 50 Hz up to 20 kHz...

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Old 16th September 2012, 08:47 PM   #978
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Choco, i like the extension you made. If it sims well i would like to build a prototype.
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Old 16th September 2012, 08:48 PM   #979
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Did match a few JFETs, and put them in the circuit in #945 - interestingly enough, got overall better DC balance and drift as expected, but THD raised quite bit: still < 0.001% @ 0dBV, 1 kHz into 30 ohm, with 2nd accounting for most of the raise. Seems that the best operating point as far as the DC balance is concerned is not the point of best AC symmetry (unless the very low figures I got a few days ago were due to some lucky cancellation effects...). Sounds anyway a little bit strange: what am I missing?

L.
Have you ran a curve trace of both to see how closely they are complimentary?
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Old 16th September 2012, 08:51 PM   #980
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If you make Q3, Q4 as folded cascodes you could couple in into the positive and negative side without criss crossing. Maybe it will have higher speed too.
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