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Old 29th August 2012, 08:55 PM   #511
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Quote:
Originally Posted by bcarso View Post
Isn't that what I said? If not, I wasn't being clear. I refer to it colloquially as a "half-thermal" noise.
If you consider the noise as comming from the collector current shot noise, the answer falls out.
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Old 29th August 2012, 09:32 PM   #512
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Radio Shack Special
npn = 2n3904
pnp = 2n3906
themally connected:
Q1 to Q5
Q3 to Q6
Q2 to Q4
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Old 29th August 2012, 10:01 PM   #513
gpapag is online now gpapag  Greece
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Quote:
Originally Posted by jneutron View Post
cheers, jn
Quote:
I have hilted in red the salient point we disagree on.
Better red than dead with this one

Quote:
The local delta T will be dependent on the heat flow between the components of interest
We certainly agree.

Quote:
not on the absolute temp.
This is the #*@!$ point on which we dissagree.

In a nutshell: Doesn’t the Newton’s Law of cooling apply?
(“The rate of a heat loss of a body is proportional to the temperature difference between the body and it’s surrounding”)


Jneutron, Scott, Jan
Thank you very much for your time and effort. I appreciate.
But I still don’t feel I can agree to this.
It is not only that I am thick. I guess I have not managed to make clear what I mean too.
I really would love to have this discussion in a bar with a few beers and drawing some lines on a hand towel (and paying the round if I am wrong) but I have to live with typing characters.
I will try to visualize:

Scenario:
Transistor a and Transistor b of same small volume and composition, distance x=200um apart, encased in a big mass of silicon (IC chip).

Current has flown through a and b and has increased their temperature.
At time t0=0 current stops flowing. Trans a has temp Ta=100 C and Trans b Tb=70 C.

At time t1=10ms I would like to compare the deltaT between a and b (deltaTab) in two different cases:
Case 1: Silicon mass temperature at t0: Ts0=20C
Case 2: Silicon mass temperature at t0: Ts0=40C

I think (intuitively) that Case’s 2 deltaTab will be larger than Case’s 1

If you will tell me that I am wrong, this time I will accept it. Promise!

George
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Old 29th August 2012, 10:06 PM   #514
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Quote:
Originally Posted by RNMarsh View Post
If you use regulated, very low z, low noise power supplies, what is the minimum psrr needed to not be an audible issue? [using topologies being discussed here].

Thx,
RNM
I think you can approximate that. If your output signal is a nominal 1V and you want -80dB S/N then whatever the power supply adds to the output should be below 100uV. Assuming the power supply has 1mV noise and ripple, 20dB PSRR would do.

jan
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Old 29th August 2012, 10:15 PM   #515
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Quote:
Originally Posted by gpapag View Post
Better red than dead with this one


We certainly agree.



This is the #*@!$ point on which we dissagree.

In a nutshell: Doesn’t the Newton’s Law of cooling apply?
(“The rate of a heat loss of a body is proportional to the temperature difference between the body and it’s surrounding”)


Jneutron, Scott, Jan
Thank you very much for your time and effort. I appreciate.
But I still don’t feel I can agree to this.
It is not only that I am thick. I guess I have not managed to make clear what I mean too.
I really would love to have this discussion in a bar with a few beers and drawing some lines on a hand towel (and paying the round if I am wrong) but I have to live with typing characters.
I will try to visualize:

Scenario:
Transistor a and Transistor b of same small volume and composition, distance x=200um apart, encased in a big mass of silicon (IC chip).

Current has flown through a and b and has increased their temperature.
At time t0=0 current stops flowing. Trans a has temp Ta=100 C and Trans b Tb=70 C.

At time t1=10ms I would like to compare the deltaT between a and b (deltaTab) in two different cases:
Case 1: Silicon mass temperature at t0: Ts0=20C
Case 2: Silicon mass temperature at t0: Ts0=40C

I think (intuitively) that Case’s 2 deltaTab will be larger than Case’s 1

If you will tell me that I am wrong, this time I will accept it. Promise!

George
In your example, you have set the base of the silicon at two different temperatures, so to get the init temps you desire, 100 and 70 will require completely different power dissipations.

In case 1, you are getting 80 rise in one, 50 rise in the second...power scaled is 8 to 5...

In case 2, you are getting 60 rise in one, 30 in the second. Power scaled 2 to 1.

The cases are different because the powers are different.

jn

ps..wish I could drink beer......I miss beer...
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Old 29th August 2012, 10:19 PM   #516
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Quote:
Originally Posted by gpapag View Post
Better red than dead with this one


We certainly agree.



This is the #*@!$ point on which we dissagree.

In a nutshell: Doesn’t the Newton’s Law of cooling apply?
(“The rate of a heat loss of a body is proportional to the temperature difference between the body and it’s surrounding”)

I see your problem, yes but consider the boundary conditions here. A slab is connected to another slab, the only boundary that matters is between them or the problem gets more complicated. In your case you are forcing temperatures (voltages) and measuring heat loss (current). In this case you are dissipating power (heat gain) and measuring the temperature difference that it creates. Both give the thermal resistance (R) across each slab.

Even a low power IC will blow up if attached to #40 wire and put in a vacuum. R is BIG.

BTW if you want real confusion do this exercise and include Peltier junctions.
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Last edited by scott wurcer; 29th August 2012 at 10:22 PM.
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Old 29th August 2012, 10:57 PM   #517
gpapag is online now gpapag  Greece
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Quote:
Originally Posted by jneutron View Post
In your example, you have set the base of the silicon at two different temperatures, so to get the init temps you desire, 100 and 70 will require completely different power dissipations.

In case 1, you are getting 80 rise in one, 50 rise in the second...power scaled is 8 to 5...

In case 2, you are getting 60 rise in one, 30 in the second. Power scaled 2 to 1.

The cases are different because the powers are different.

jn

ps..wish I could drink beer......I miss beer...
Case 1 (Silicon mass temperature at t0: Ts0=20C)is for a typical case of an IC in ambient temperature.
Case 2: (Silicon mass temperature at t0: Ts0=40C)is for the case of an IC intentionally control heated.

If you think that Ta=100C and Tb=70C are unrealistic, please put reasonable numbers.

I sympathise.
I had to stay away from beer for 5 years after a stomach operation. (I was told that after the operation ).
Now I drink again, not a lot but I enjoy it.

George
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Old 29th August 2012, 11:24 PM   #518
RNMarsh is offline RNMarsh  United States
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Default Bingo!

Quote:
Originally Posted by janneman View Post
I think you can approximate that. If your output signal is a nominal 1V and you want -80dB S/N then whatever the power supply adds to the output should be below 100uV. Assuming the power supply has 1mV noise and ripple, 20dB PSRR would do.

jan
Bingo! That's how I figure it, too.

Dont sweat the PSRR too much if you use good, quiet multiple reg supplies and best practices in grounding.

Last edited by RNMarsh; 29th August 2012 at 11:27 PM.
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Old 29th August 2012, 11:37 PM   #519
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Default Preliminary results on the 2SK2145 dual

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Originally Posted by bcarso View Post
Someone should test a few of the duals. If they isolate the halves (before hardwiring the channels together) the same way they do in the obsoleted parts like the 389, there are no parasitic diodes to conduct other than via reverse leakage (I tested this with the 389, facilitated by their bringing out a lead for the substrate --- which they then tell you to float ). I think they just have blinkers on as far as the possible different configurations. But maybe not ---perhaps the hard wired "sources" are part of a structural change to simplify isolation. Testing will tell.

It's interesting that the model published for the BF862 shows markedly different parasitic (i.e., "contact") resistances in series with the designated "drain" and "source". However, when I tested a few there was virtually no difference in on resistance for normal or reversed connections. BTW those parasitic resistances start to become important at high drain currents and limit the already-slow rate of improvement of transconductance and noise reduction.
Through the kindness of Wayne I received some SK2145 duals today. I hooked one up as best I could manage on a 5 lead SOT package and did some testing on different configurations besides the standard differential pair.

First noted: a marked asymmetry (the most I've ever seen) between "forward" and "reverse" on resistance. The two halves were closely matched, but forward was about 120 ohms and reverse about 90.

I then attempted the source follower loaded by a constant current source. I had 8.2M in the gate of the input. +5V and -5V rails. So the lower I source was hooked up "backwards", with its drain tied to its gate and -5V. Idss about 2.7mA at ~5V.

It worked but had a large offset, about -1.5V. Ouch. But was it due to the asymmetry or what? I grounded the input gate through a clip lead and got 60MHz oscillations. I grounded it with 820 ohms. Offset now merely a few millivolts. I grounded it again through the 8.2M with 33nF across. Same large offset. Conclusion: yes, Toshiba did not use the same style structure for this dual as for the old lines. Too bad. The offset due to gate current means the leakage from whatever to the gate lead under these conditions is about 180nA. Not good, although usable in some apps.

Moved on to the other configuration of interest: loading the drain of a common-source amp with a matched constant current source. Same rail voltages. 12k load resistor to ground. Top FET with gate tied to its source.

Result: gain of 100 with only a small offset! By chopping between 100k as the lower gate resistor and 820 ohms, I am just able to see some small change in the output voltage. It will require a good deal better setup to quantify it, but rough estimate is that the input gate leakage is of order 2nA, maybe better. Much better in any case than 180nA, making this configuration promising for use as a gain stage.
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Old 29th August 2012, 11:58 PM   #520
gpapag is online now gpapag  Greece
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Quote:
Originally Posted by bcarso View Post
BTW, the noise contribution from that "resistance" is due to shot noise in the current referred to the input as a voltage noise density. Since the transconductance goes up directly with current and the shot noise goes as the square root, for low source impedances the overall noise goes down with increasing current, to a point that, among other things, is limited by the real thermal noise of the base spreading resistance. The contribution of the shot noise/transconductance makes the expression for the re contribution look like about that of a real resistor half the value of re, which is nice.

It's funny to see people using very-low base resistance transistors at moderately low currents. The Marshall Leach-style common-base MC stepup circuit is an example --- but in his defense, he was also interested in prolonging battery life.


The current/noise issue is pointed out very clear here (pages 1-2)
http://www.ti.com/lit/an/snoa626a/snoa626a.pdf

(I hope that after the merging, TI will decide to make LM194/394 available again)

George
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