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Analog Line Level Preamplifiers , Passive Pre-amps, Crossovers, etc.

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Old 27th August 2012, 06:14 AM   #311
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No, please do NOT use those devices: Use J113, J175 devices. They are available, have high enough Idss to give peak drive current, and are the equivalent of the E113, etc which was just a different package. (same die)
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Old 27th August 2012, 06:17 AM   #312
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Hitsware, the N-N and P-P match are most important for low DC offset, without a servo.
The absolute Idss of the N-N can be somewhat different from the P-P pair because the SINGLE resistor bias FLOATS off ground and will find the best compromise automatically.
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Old 27th August 2012, 06:46 AM   #313
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John,

Would you care to comment on the topology in post#306 ?
Please ignore the devices. They are of course not up to date.

Some specific questions :

1. Is the current mirror of the first stage really necessary ?
Could we not just tape the drive voltage to the 2nd stage off the resistors (if necessary different values) ?

2. Cascode vs no cascode for 2nd stage ?
Are the cascode there for open loop frequency response reasons ?


Thanks,
Patrick
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Last edited by EUVL; 27th August 2012 at 06:48 AM.
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Old 27th August 2012, 12:38 PM   #314
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Good morning everyone. Another day, another schematic.
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Old 27th August 2012, 12:42 PM   #315
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This is just so I don't get yelled at by John. Performance is a little better, but there's a really nasty spike at 15MHz.
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Old 27th August 2012, 01:12 PM   #316
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Quote:
Originally Posted by bcarso View Post
I wish you'd stop calling me Surely.

Quote:
Originally Posted by bcarso View Post
(although until Scott posted I had no idea what they really did, but knew that positional adjacency information was either lost or not taken into account).
At wafer probe, the probe setup can be used to test adjacent die, and they can setup the inker to either mark the good pairs, or mark those which do not meet requirements. Subsequent auto pick and place can easily visually detect either lack of an ink dot, or a specific color.

After test, the wafer is first bonded to a sticky plastic film, the either scribed and broked like Scott mentions, or the wafer is sawcut between the die to the film as I've been involved with. The "expanded" I mentioned is a film which can be stretched, and a rounded probe under the die can push up so that the film releases the die to the vacuum pick.

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Originally Posted by scott wurcer View Post
What's funny is that back in 1974 they had a slice of a huge steel rod about 4" in diameter that they rolled over the wafer to break all the scribes.
My work back in the day was with mil spec hybrids, so laser scribing was a definite no-no...we had to pass PIND testing.

jn
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Old 27th August 2012, 01:16 PM   #317
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How can the die be attached to the collector/drain/source?
How many layers are in that connection?
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Old 27th August 2012, 01:30 PM   #318
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Dirk, maybe the peak goes away when you make an output inclusive compensation.
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Old 27th August 2012, 01:37 PM   #319
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How can the die be attached to the collector/drain/source?
How many layers are in that connection?
A wafer backside is generally the collector for power zistors, and drain for power fets.

Small signal devices can be isolated from backside by a reverse biased pn junction, or even a grown isolation like silicon nitride.

My work with individual or dual transistors/fets had only the one layer of aluminum in a 2-d pattern.. MSI and LSI of course had multiple layers with crossovers. Copper traces weren't around in my day, we had to fight the raptors..

John
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Old 27th August 2012, 01:51 PM   #320
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Quote:
Originally Posted by Joachim Gerhard View Post
Dirk, maybe the peak goes away when you make an output inclusive compensation.
Yeah, about 13pF put across the feedback resistor brings the spike down to about 6dB (from 15 or so). Distortion is slightly worse though. Someone else needs to step up and start modeling. Too much yapping about dies and other things and not enough modeling!
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