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Old 7th January 2013, 12:45 PM   #2581
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I checked it out, and was rather disappointed when I read that:
"
The greatest benefit from multiple cores is achieved when running Monte Carlo analyses and other multiple analysis modes. This applies to both SIMetrix and SIMPLIS simulators. For this application, typical performance benefit of about 75% of the core count can be achieved. So for 4 cores a Monte Carlo run may execute about 3 times faster. The SIMetrix simulator can also exploit multiple cores to gain a speedup for single runs, but the performance benefit achieved is much more modest and typically there is little benefit in having more than about 4 cores
"

More than 4 cores are thus not needed for single runs in TRAN :-(

I stay with MicroCap10.


Quote:
Originally Posted by PHEONIX View Post
Hello Richard,

If you want a good simulator that will run in linux try simetrix at the link below, its available in various versions and is a serious simulator. It also has the option of being command line driven.

Analog, mixed signal circuit simulation software tool, SIMetrix, SIMPLIS, Micron VX, DVM

In my opinion its better than Microcap because its unaided convergence is superior which means it crashes fewer times on circuit simultions. But Microcap is an excellent simulator and there are many users on this forum who are quite productive with it Edmond Stuart comes to mind.

Arthur
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Old 8th January 2013, 04:52 PM   #2582
RNMarsh is offline RNMarsh  United States
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4 cores and 3X faster.... but also with fewer hangups. So 8 cores sounds about right for me. As cost of cores comes down and/or becomes more popular, the software developers make further improvements. So a few more cores is a good thing. Guess I'm looking for an 8 core for now and for its future advantage. Thx-RNMarsh
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Old 10th January 2013, 02:18 PM   #2583
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For J7 and J8, can I use 2n4416A/mpf3821? I have a bunch already matched. Thanks, Ray
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Old 10th January 2013, 11:50 PM   #2584
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Quote:
Originally Posted by grhughes View Post
For J7 and J8, can I use 2n4416A/mpf3821? I have a bunch already matched. Thanks, Ray
I presume you are referring to J17 and J18 (the input JFET's) in the diagram attached to Post 2409.

The MPF3821's specified Idss is too low (0.5 mA guaranteed minimum) to use in this circuit without extensive redesign of the entire biasing scheme. Those input devices require an Idss of AT LEAST 5.0 mA.

The 2N4416A satisfies the Idss requirement, but the forward transconductance is lower than the suggested BF862 by a factor of about 8:1. Without checking it out in simulation it's probably safe to say that the amplifier WILL amplify, but the overall performance will be measurably lower.

One interesting characteristic of this architecture that shows up in several posts along this thread is that the design seems to be relatively immune to variations among the active devices, so it may be interesting to try a pair of 2N4416A's just for the experience.

Dale
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Old 11th January 2013, 02:16 AM   #2585
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"it may be interesting to try a pair of 2N4416A's just for the experience."

Thanks! I was thinking about the upper cascode devices rather than the input jefets I'll stick with the recommended BF862 devices. I just had these on hand. Ray
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Old 11th January 2013, 03:17 AM   #2586
RNMarsh is offline RNMarsh  United States
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Quote:
Originally Posted by dchisholm View Post
One interesting characteristic of this architecture that shows up in several posts along this thread is that the design seems to be relatively immune to variations among the active devices, so it may be interesting to try a pair of 2N4416A's just for the experience.

Dale
is it the architecture or the very high feedback that makes it insensitive to device variations? How much does each contribute to that characteristic? Thx-RNMarsh
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Old 11th January 2013, 03:49 AM   #2587
jcx is offline jcx  United States
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well you could try Bode's sensitivity analysis - likely even taught in EE programs when you were in college

Cherry has a good paper on the subject that takes a step into nonlinearity contributions (article tests the developed estimation math against actual Hardware)

Cherry’s “ESTIMATES OF NONLINEAR DISTORTION IN FEEDBACK AMPLIFIERS” JAES V48#4 2000 p299-313 provides a method of calculating individual component distortion mechanisms contribution to overall distortion of a amplifier, more importantly it gives a intellectual framework for reasoning about distortion and feedback in a feedback amplifier.
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Old 11th January 2013, 04:31 AM   #2588
RNMarsh is offline RNMarsh  United States
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nah. I dont want to do that. i just want an answere from one who already knows the general answere for this topology. The assertion was that it was the topology, as i understood it. Did one do those calc against other topologies? For example in most any topology enough degeneration R will give similar insensitity to device parameters ... regardless of topologiy. A lot of gnfb can do the same thing as far as end results (distortion) is concerned... again, regardless of topology. I'm just messin' with ya... making a trivial point is all.

Thx-RNMarsh

Last edited by RNMarsh; 11th January 2013 at 04:39 AM.
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Old 11th January 2013, 01:04 PM   #2589
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Quote:
Originally Posted by RNMarsh View Post
is it the architecture or the very high feedback that makes it insensitive to device variations? How much does each contribute to that characteristic? Thx-RNMarsh
The biggest problem with the 4416 is the highish Vp so cascoding it is less simple. The pairing of a low Vp input device and a high Vp cascode is the easiest (just tie the gate back to the source).

The gm at 5mA of the 4416 is also lower, but the intent of this design was to get the most out of a single gm-C gain stage so there is latitude to just adjust C and see what you get. To repeat one of the points of a discrete circuit is the ability to custom compensate for each location.

I tried in the simplest way to compensate for base current errors and dynamic Ccb errors in the bipolars that's why I think there is some desensitivity to device selection (within limits of course).

Little slow right now since I seem to have a touch of the flu but I got the output board through the reflow and all seems well, bias trimmed right up and hope to repeat the open-loop performance verification.
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Old 12th January 2013, 03:41 PM   #2590
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Thanks Scott! Take care of that flu! Ray
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