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Old 24th August 2012, 10:27 PM   #231
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Bear,

JFET Input gm stage. John's example here uses this.

Dave
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Old 24th August 2012, 11:20 PM   #232
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Here's a nice input diff stage device, but doesn't give its best performance with +/- 15 VDC supplies: (and p-channel devices aren't possible in this part of the galaxy, at least)

http://www.triodeel.com/6dj8_p3.gif

Thanks,
Chris

Last edited by Chris Hornbeck; 24th August 2012 at 11:23 PM.
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Old 24th August 2012, 11:50 PM   #233
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Quote:
Originally Posted by fitzfish View Post
Bear,

JFET Input gm stage. John's example here uses this.

Dave
Sorry... lost in space again... basic LTP... thinking of the drains tied in my head... my brains tied in knots, same thing.

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Old 25th August 2012, 05:39 AM   #234
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Scott,

A SMD dual JFET in SOT23 is too good for me to give up, so I went back to the Toshiba website.
It says (see attached) internal connection common source.

So it can at least be used for input LTP.

Toshiba never says whether their FETs can be used with D/S swap.
All the ones I tried can, even though some has a slightly different Idss when reversed.
But this is solvable even if the lower FET has lower Idss when reversed.
Just tie a resistor or a CRD from Vout to the negative rail.

So I am still on for this one.

I think Dave posted the wrong link.
Here is the link to John's circuit using N-JFETs as input.

Discrete Opamp Open Design

And I also put it here.
I'll do a PCB layout in SMD. I like this.


Patrick
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File Type: png 2SK2145 Common Source.png (18.7 KB, 461 views)
File Type: jpg J Curl Discrete Opamp 1.jpg (190.9 KB, 472 views)
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Old 25th August 2012, 06:26 AM   #235
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Hi Patrick,

Just an example for the LTP application... I agree this one John posted with MOSFET VAS is much more interesting. Looking forward to it.

Dave
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Old 25th August 2012, 07:37 AM   #236
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John,

Would you be so kind to pick a Dual P-MOS for the second stage, before we get Spice models for simulation ?

(Had to add the last one separately as I exceeded max file size for Zip.)

Thanks,
Patrick
Attached Files
File Type: zip TOS Dual PMOS SMD.zip (846.5 KB, 44 views)
File Type: pdf SSM6P36FE Dual PMOS TOS SMD.pdf (189.9 KB, 70 views)
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Old 25th August 2012, 07:39 AM   #237
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And again for Dual N-MOS for the output stage please.


Patrick
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File Type: zip TOS Dual NMOS SMD.zip (905.4 KB, 37 views)
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Old 25th August 2012, 07:43 AM   #238
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Patrick, John,

My suggestion for second stage dual P mosfet-

Dave
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File Type: pdf FDG6304P.pdf (104.1 KB, 72 views)
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Old 25th August 2012, 07:47 AM   #239
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Patrick, John,

My suggestions for buffer dual N mosfet- 6301 is tiny. 6303 has higher gain and power dissipation.

Dave
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File Type: pdf FDC6303N.pdf (78.3 KB, 44 views)
File Type: pdf FDG6301N.pdf (103.6 KB, 33 views)
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Old 25th August 2012, 01:21 PM   #240
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What would you expect from a configuration like this?

The input stage does not need additional components for biasing.
It will offer high input impedance and low noise.
R1 and R2 allow adjustment of bias independently from adjustment
of gain and degeneration which is solved by R3 and R4....
Last but not least you could use such an OP amp for voltage feedback configurations and current feedback applications as well. In current feedback applications one could use the nodes of R1 as current feedback inputs, or center tap R1...
All the rest of the circuit is mostly standard.
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