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Old 24th August 2012, 08:13 PM   #221
bcarso is offline bcarso  United States
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Originally Posted by scott wurcer View Post
Typically they're scribed on a sheet of heat activated sticky plastic and stretched. Now they would probably use a vacuum pencil pick and place after that.

The same die dual issue would be what is the substrate, I thought it might be the back gate so isolated duals would have to be two die. We always bought them that way.

EDIT Sorry EUVL the FET's were drawn funny, and some symbols show the arrow at the drain.
I ran across a company in Utah making four-terminal JFETs with front and back gates. They seemed to be focusing on the X-ray spectroscopy biz to begin with, branched out into FETs. One "package" shown was a "nailhead". Your business to select a low-loss dielectric
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Old 24th August 2012, 08:22 PM   #222
coluke is offline coluke  Italy
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The paper was in the Hewlett-Packard Journal (...)
February 1971 issue: http://www.hpl.hp.com/hpjournal/pdfs...Fs/1971-02.pdf

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Old 24th August 2012, 08:29 PM   #223
bcarso is offline bcarso  United States
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How nice that is available! Thanks for finding it.

Brad
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Old 24th August 2012, 08:43 PM   #224
coluke is offline coluke  Italy
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How nice that is available! Thanks for finding it.
I must confess I'm addicted to HP journal

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Old 24th August 2012, 08:44 PM   #225
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How nice that is available! Thanks for finding it.

Brad
All math no simulator, interesting look at old school analysis. The old Teledyne publications were also good in this respect.
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Old 24th August 2012, 08:55 PM   #226
coluke is offline coluke  Italy
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All math no simulator,
On a 9100A - a ~20 kg RPN programmable calculator with a 196 steps wide program memory

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Old 24th August 2012, 09:31 PM   #227
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Scott -- how would you modify your input to apply negative common-mode feedback?
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Old 24th August 2012, 09:37 PM   #228
RNMarsh is offline RNMarsh  United States
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Originally Posted by bcarso View Post
I ran across a company in Utah making four-terminal JFETs with front and back gates. They seemed to be focusing on the X-ray spectroscopy biz to begin with, branched out into FETs. One "package" shown was a "nailhead". Your business to select a low-loss dielectric
Are there dual gate jFET's similar to a dual gate MOSFET?
-RNM
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Old 24th August 2012, 10:07 PM   #229
bcarso is offline bcarso  United States
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Are there dual gate jFET's similar to a dual gate MOSFET?
-RNM
No, those were front and back gates. Not a cascode structure.

EDIT: Actually I think there were some integrated cascode duals, but they didn't being out all the connections.

Last edited by bcarso; 24th August 2012 at 10:30 PM.
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Old 24th August 2012, 10:11 PM   #230
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2SK2145, the ratings/specs are for devices in parallel operation or single devices?

Afaik not all jfets can be run "backwards"... most?

...then the question is the IDSS group 1/2 of the parallel IDSS or??

So, what is the application for a dual jfet with the sources tied together - or why not internally wire them in parallel and offer the device as a "single"?
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