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Old 24th August 2012, 06:58 PM   #211
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Thanks Brad, Wayne.

Are we talking adjacent die? perhaps 5% or less matching?

Nice, small package for an smt discrete opamp LTP. Beats the SO8 from LSK.

Dave
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Old 24th August 2012, 07:14 PM   #212
bcarso is offline bcarso  United States
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Quote:
Originally Posted by fitzfish View Post
Thanks Brad, Wayne.

Are we talking adjacent die? perhaps 5% or less matching?

Nice, small package for an smt discrete opamp LTP. Beats the SO8 from LSK.

Dave
Yes, they mention 2% for some of the parameters. A great idea; formerly they just sliced and diced and dumped into a big hopper before packaging, I guess. Having things off the same wafer was better than nothing, but this is a lot better.
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Old 24th August 2012, 07:25 PM   #213
EUVL is offline EUVL  Europe
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Yes, ideal part.

Same package as the BF862, but with two FETs on one die.
Noise a bit high, and could do with a bit more Yfs.
But then you can't have it all ......


Patrick
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Old 24th August 2012, 07:28 PM   #214
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Quote:
Originally Posted by EUVL View Post
Yes, ideal part.

Same package as the BF862, but with two FETs on one die.
Noise a bit high, and could do with a bit more Yfs.
But then you can't have it all ......


Patrick
The data sheet I downloaded has the gates tied together, limited use?
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Old 24th August 2012, 07:33 PM   #215
EUVL is offline EUVL  Europe
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Datasheet Version 2007-11-01, tied source and not tied gates ?
Still useful for input LTP ?

http://www.semicon.toshiba.co.jp/eng...485_13588.html


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Last edited by EUVL; 24th August 2012 at 07:49 PM.
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Old 24th August 2012, 07:40 PM   #216
EUVL is offline EUVL  Europe
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2SK3320. Same electrical spec.
Even smaller package.

2SK3320?Junction FETs (Single/Dual)?TOSHIBA Semiconductor & Storage Products Company


Patrick
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Old 24th August 2012, 07:44 PM   #217
EUVL is offline EUVL  Europe
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As most FETs are Drain / Source reversible, one can even use this as a Source Follower for the output stage.

For example :

Pin 1 = +Vs
Pin 2 = +Vout
Pin 3 = -Vs
Pin 4 = -Vs (via gate stopper)
Pin 5 = +Vin (via gate stopper)


Patrick
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Old 24th August 2012, 07:48 PM   #218
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Quote:
Originally Posted by bcarso View Post
formerly they just sliced and diced and dumped into a big hopper
Dumped into a big hopper??? Shirley you jest..

I'da thunk either an expanded wafer, or waffle pack..

jn
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Old 24th August 2012, 07:53 PM   #219
RNMarsh is offline RNMarsh  United States
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Default good idea -

Quote:
Originally Posted by EUVL View Post
As most FETs are Drain / Source reversible, one can even use this as a Source Follower for the output stage.

For example :

Pin 1 = +Vs
Pin 2 = +Vout
Pin 3 = -Vs
Pin 4 = -Vs (via gate stopper)
Pin 5 = +Vin (via gate stopper)

Patrick
That is a good concept... useful and practical suggestion.
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Old 24th August 2012, 07:55 PM   #220
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Quote:
Originally Posted by jneutron View Post
Dumped into a big hopper??? Shirley you jest..

I'da thunk either an expanded wafer, or waffle pack..

jn
Typically they're scribed on a sheet of heat activated sticky plastic and stretched. Now they would probably use a vacuum pencil pick and place after that.

The same die dual issue would be what is the substrate, I thought it might be the back gate so isolated duals would have to be two die. We always bought them that way.

EDIT Sorry EUVL the FET's were drawn funny, and some symbols show the arrow at the drain.
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Last edited by scott wurcer; 24th August 2012 at 08:03 PM.
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