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Old 24th October 2012, 02:17 AM   #1861
fas42 is offline fas42  Australia
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Thanks for the clarification ...

Frank
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Old 24th October 2012, 02:18 AM   #1862
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Quote:
Originally Posted by kgrlee View Post
Anyone know if LTspice accepts Level 3 FET models whatever these are? I note it complains of

* Unrecognized parameter "jd" -- ignored
* Unrecognized parameter "js" -- ignored

In Scott's j305 & bf862 models
Typo should be mjd, mjs they don't matter that much anyway.
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Old 24th October 2012, 02:44 AM   #1863
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Originally Posted by scott wurcer View Post
The distortion characteristics due to Vds are all wrong.
An argument for cascoding?

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Old 24th October 2012, 02:53 AM   #1864
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Cascoding has a variety of benefits, among them simplifying models a bit.

One thing not often noticed: the input Z of the cascoding part is finite. Even when it is a bootstrapped cascode, the reduction of Miller C is limited by this, and the load in the upper device is significant in determining this Z.
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Old 24th October 2012, 03:17 AM   #1865
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With differential input pairs - cascoding with bipolars seem to have advantages over jfets. In the past, I have found simple neutralizing techniques do similar work to reduce (cancel) C. And, you can cancel completely the Miller C by added input c with series R to get same value. Little used techniques that dont cost much but are very circuit specific. Anyone tried these other methods? Comments, pls. -Thx RNM

Last edited by RNMarsh; 24th October 2012 at 03:19 AM.
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Old 24th October 2012, 03:30 AM   #1866
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Originally Posted by RNMarsh View Post
With differential input pairs - cascoding with bipolars seem to have advantages over jfets.
Bipolars at the same current will always trump JFETs or DMOS parts, unless the latter are huge. This is true in particular if there is a lot of voltage swing/gain at the upper collector. An intriguing question: under what conditions is a given part or set of paralleled parts optimal for reducing the overall input capacitance of the cascoded stage? I.e., how huge is huge?

This isn't offered rhetorically btw.
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Old 24th October 2012, 03:42 AM   #1867
RNMarsh is offline RNMarsh  United States
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With some input series R to work with -- maybe similar value to stage load R --- the effective output C formed by the stage gain when matched with input C, will cancel. that is add more input c to equal the gain stage output C. The input and output being of opposite phase will cause any signal thru the C's to cancel.... thus making the C seem to not be there or zero equivalent. No cascoding needed and distortion from this source is reduced. [if you can have more input C for your appl]. Just a point of conversation. ideas.
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Old 24th October 2012, 03:46 AM   #1868
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Default Simulator

Hello Brad

What simulator do you use.

Regards
Arthur
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Old 24th October 2012, 03:50 AM   #1869
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For people's information, I just tried the model of the BF862 that's being used in LTspice, and it does add a gentle curve, slope decreasing towards zero gate voltage, to the transconductance characteristic; a simple, minimal spec'd set of parameters for a JFET just traces a straight line, otherwise.

Frank

Last edited by fas42; 24th October 2012 at 03:56 AM.
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Old 24th October 2012, 03:57 AM   #1870
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Hello Brad

What simulator do you use.

Regards
Arthur
Circuitmaker Pro something. No longer supported afaik, and I have devised many patches around its bugs.
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