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Old 24th August 2012, 03:50 PM   #161
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Discrete design offers advantages that IC design limits. IF you HAVE to keep within IC limits or model after IC's, then why duplicate the effort? Just get the IC.
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Old 24th August 2012, 03:53 PM   #162
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Quote:
Originally Posted by scott wurcer View Post
No claims made other than output current, bias, etc. diy'ers feel good about doing it themselves i.e. fun.
Also, DIYers can close an internal feedback loop, before the buffer, and compare results.
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Old 24th August 2012, 03:53 PM   #163
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I will check back in a year or so... maybe by then ONE design will finally emerge...

nah.

but let's assume that "we" arrive at say 6-12 topologies reduced to practical design (seems like this is more likely than a single design agreement?), now what?

Do they get sim'd and selected?
Criteria?

Or sim'd, say top 3-6 culled (based on those "criteria"?), and then some prototype builds followed by what? Actual tests for specs? Listening tests??

Or maybe that is enough?

Go to PCB group buys and see what people say?

We can burn the discrete through-hole vs. SMT vs. both bridge down the road...

Just looking ahead to see where this needs to go. No GPS here.

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Old 24th August 2012, 03:56 PM   #164
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by scott wurcer View Post
PMA's circuit looks like two CFA inputs looking at eachother, it lends itself very well to full differential connection.
[...]
Yes, but its a pity that with BJT you need lots of biasing stuff: I1, 2, 3, 4 and Q1, 6, 12, 13, wich you would not if P and N Channel JFET's were allowed.....
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Old 24th August 2012, 03:57 PM   #165
bcarso is offline bcarso  United States
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Quote:
Originally Posted by scott wurcer View Post
PMA's circuit looks like two CFA inputs looking at eachother, it lends itself very well to full differential connection.

For that matter that simplified 844 made with discrete duals could be tuned up nicely for several applications. I think there are cheap SMT dual's in the BXXXX series. That's 8 SOT6's and an output pair and you have access to all nodes so you play with Charles Hansen's ideas.
NXP and Diodes Inc. at one time at least made duals that were two isolated chips plucked from adjacent locations on the wafer, with usually not much by way of guarantees but likely pretty decent matching.

I once talked to Diodes about what the breakdown voltage was between the chips. The guy's first response was But they are isolated! There's no way you can have breakdown!

I said Oh good! So I can run them at 10 kilovolts difference in potential??

At that point he got it, and conceded that they had no idea
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Old 24th August 2012, 03:58 PM   #166
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Quote:
Originally Posted by PMA View Post
One more.
One more Blowtorch!
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Old 24th August 2012, 04:05 PM   #167
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Then the next question - for those of us who must follow the opera by reading the libretto - references, papers and texts to stare at blankly in the vain hope of discovering only some of these complexities...

this is one I discovered in the first edition years back... I don't pretend to have digested it all by any means:

Bipolar and MOS Analog Integrated Circuit Design (Wiley Classics Library)
By: Alan B. Grebene

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PS. when I first saw this book, I thought to myself - "myself, how the heck did this guy learn all of this, when all the other texts I have seen don't even scratch this surface at all??" (ie. where are they keeping the real information hidden? Do you have to reinvent the wheel for yourself?)
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Last edited by bear; 24th August 2012 at 04:08 PM.
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Old 24th August 2012, 04:12 PM   #168
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More practical configuration, but still an all fet design.
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Old 24th August 2012, 04:21 PM   #169
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john curl,
Your so practical, and this discussion doesn't seem to have anything to do with practicality. I guess we can just reinvent the wheel until we get a square one and then decide that it won't go around any better than what exist, but that seems to be the point of this project. Just to try something and see what happens.
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Old 24th August 2012, 04:31 PM   #170
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Quote:
Originally Posted by bcarso View Post
NXP and Diodes Inc. at one time at least made duals that were two isolated chips plucked from adjacent locations on the wafer, with usually not much by way of guarantees but likely pretty decent matching.

I once talked to Diodes about what the breakdown voltage was between the chips. The guy's first response was But they are isolated! There's no way you can have breakdown!

I said Oh good! So I can run them at 10 kilovolts difference in potential??

At that point he got it, and conceded that they had no idea
70 volts per mil of physical isolation if it is a hermetically sealed hybrid. I assume they enclosed dry nitrogen during lid one shot weld..

jn
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