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Old 6th October 2012, 01:28 AM   #1551
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I'm post the latest schematic tomorrow and make sure the lines are all there.
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Old 7th October 2012, 03:15 AM   #1552
RNMarsh is offline RNMarsh  United States
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Default Using local degen -

For power amps and line level amps; Some jFEts have a pretty high Vp - several volts and low capacitance.

Adding local nfb/degeneration can pretty much take the Gm out of the picture and makes matching easier.

[I made it!! ... Its Sunday - sitting on the 15th floor in downtown Bangkok, Thailand at this time.]

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Old 7th October 2012, 08:35 AM   #1553
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Quote:
Originally Posted by fas42 View Post
I'll be calling that version SW-OPAn, the other SW-OPAc, unless someone has a better thought ...
If the circuit is from eg #1380, perhaps SW-OPA1380fas42 might be good.

This would show who did the model too. And please put the information in the *.asc file as a text line too. And the date.
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Old 7th October 2012, 08:59 AM   #1554
dadod is offline dadod  Croatia
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Quote:
Originally Posted by kgrlee View Post
If the circuit is from eg #1380, perhaps SW-OPA1380fas42 might be good.

This would show who did the model too. And please put the information in the *.asc file as a text line too. And the date.
I think better is to put *.asc file together with the models file in one zip file. When a models are on the *.asc it's not easy to read, to many diffetent text screening the schematic.
dado
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Old 7th October 2012, 09:44 AM   #1555
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Quote:
Originally Posted by dadod View Post
I think better is to put *.asc file together with the models file in one zip file. When a models are on the *.asc it's not easy to read, to many different text screening the schematic.
Definitely!

But I was referring to simple info like
- who's circuit
- who did this SPICE file
- date when it was done/last edited
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Old 7th October 2012, 11:06 AM   #1556
miklos is offline miklos  Canada
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The post # pretty much covered it up to now.
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Old 7th October 2012, 12:04 PM   #1557
fas42 is offline fas42  Australia
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I agree it's a good idea to document as kgrlee suggested ... everyone has their own ways of doing things, and I tend to put everything on the one diagram, and scroll to the appropriate bits. One thing that has always bugged me with LTspice is that it keeps deciding what zoom level to show the schematic at, when I set up the views in the way to suit me, so I've worked out a couple of tricks to get around that ...

In the meantime, I'm waiting for Scott to post his next version, no point in adding to the confusion by introducing something which will be out of date in a few hours ...

Frank
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Old 7th October 2012, 02:15 PM   #1558
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Latest schematic, I added input cascodes and tied the bias setting current surces together at the drains so only one cascode would be needed (for operation at high supply voltages). The two .1uF capacitors no longer seem to do anything (it could have been a simulation artifact) so they are gone. This should be fine gain of five and up, still looking at lower gains.

Cascodes are J111 or a depletion mode MOSFET as we discussed.
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Old 7th October 2012, 02:58 PM   #1559
EUVL is offline EUVL  Europe
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Should I use this for PCB layout ?


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Old 7th October 2012, 03:32 PM   #1560
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Quote:
Originally Posted by scott wurcer View Post
Latest schematic, I added input cascodes and tied the bias setting current surces together at the drains so only one cascode would be needed (for operation at high supply voltages). The two .1uF capacitors no longer seem to do anything (it could have been a simulation artifact) so they are gone. This should be fine gain of five and up, still looking at lower gains.

Cascodes are J111 or a depletion mode MOSFET as we discussed.
Hi Scot,
What are the NPN and PNP transistors?
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