Ewww.
This is even worse:
Dan Pashman: Veggieducken: Why I Invented This Vegetarian Thanksgiving Centerpiece Masterpiece
I'm doing a celeriac/Yukon gold gratin and a lentil/wild mushroom potage.
This is even worse:
Dan Pashman: Veggieducken: Why I Invented This Vegetarian Thanksgiving Centerpiece Masterpiece
I'm doing a celeriac/Yukon gold gratin and a lentil/wild mushroom potage.
Don't think so- I have a recipe posted on my website.
Gratin of Celery Root and Yukon Gold Potatoes
Superb with white Burgundy (we're cracking our last bottle of '93 Niellon Batard).
Gratin of Celery Root and Yukon Gold Potatoes
Superb with white Burgundy (we're cracking our last bottle of '93 Niellon Batard).
A friend of mine raised turkey's one year, damn they are stupid. The red fox did not mind however. When he got the little turkeys, he had to get little chickens as well, so that they would teach the turkeys what the food/water bowls were for.
Also found out pigs are smarter than dogs. My farming experiences.
Also found out pigs are smarter than dogs. My farming experiences.
Back off- or on-topic, depending on your inclination. The posted circuit uses a p-JFET, it's only simulation circuit and the JFET models may be unrealistic - but still, it sims with remarkably low THD20 of around -120 dbr at 4V amplitude into 600R. This is about the best I've ever managed with just 12 actives.
Attachments
Looks good Linux.
What's THD20?
Can you post your BJT & FET models please. Where are they from?
THD20: Total Harmonic Distortion at 20 kHz, from SPICE transient analysis.
The FET and BJT models were mostly downloaded from the NXP website a while ago. The 2sk170bl model is from forum member apparatusonitus, and the 2sk246 model (possibly unrealistic) is from madlabo (japan).
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It would appear Idss for the output JFETs is a tad low for the desired output current swing? Or are you intentionally allowing for significant forward gate bias?
J175 also seems to work fine, and the samples I've measured have Idss in the 12 to 24 mA range - I probably need to hand-select those with Idss > 20 mA or so.
I wonder if there's any other high-Idss pair that will work here. J310 comes to mind, but its Vds is a bit low.
In the old process 51 N channel family, the 2N4391, bracketed for high Idss, has the advantage of a metal case and a power rating of an astonishing 1.8W iirc when that case is held at 25C. The somewhat similar P part 2N5114 can be similarly heat-sunk when the gate is tied to the case.
It appears both parts are being made by Linear Integrated Systems, who however only gives an ambient rating of 500mW for the P part and evidently does not tie the gate to the case like the 4391. Older 5114s definitely had the gate connected to the case.
Thanks - however, these TO18 JFETs seem to be moderately expensive and/or available only on EBay.
An alternate approach is to use a JFET-BJT Douglas Self Type-II follower at the output, at the cost of two additional BJTs, which can however be high-current, like the bc639/bc640 pair. This works in the sim, giving up only about 5 dB in THD20, which can perhaps be regained by carefully optimizing the output stage bias currents and/or using a premium Japanese pair like the 2sb649/d669. This would be ideal for the professional 6-pin API2520 footprint and /- 24V rails.
A random thought - the BJT output pair can be on a base PCB with the API2520 pinout, into which the rest of the circuit with the DIP8 pinout can be plugged, to create a professional, high-current version.
The more compact DIP8 portion can be used independently as a low-rail, lower current version for line-level upgrades, etc.
Edit: This may require a few jumpers on the DIP8 portion to reconfigure some of the pins, depending on whether it is to be used independently or plugged into the API2520 base with the high-current output pair.
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linux, which SPICE do you use? Obviously not LTspice.
Can you post your SPICE model?
Actually, I'm using LTSpice III Version 2.21r. It's 5 years old, but works for me under Wine/Linux, and I don't want to break things silently by upgrading.
I posted the models I used earlier - just paste them into standard.jft and standard.bjt (renaming some models if necessary) and you should be good to go.
Try J111/J175 with 100R source degeneration each for the output stage - it seems to work well.
If you don't like the 2sk246 models for the J1/J3 cascodes, try the default LTSpice 2n4393 model, which gives results which are within a few dB.
If the 2sk170bl model looks too optimistic, please post a more realistic model or suggest alternative FETs. I'd prefer to use the 2sk170 in the real prototypes since I can get them in both BL and V grades for 40c unmatched and 80c matched off EBay.
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For the output - J74 will parrallel - match IDSS within 10% of the K170s and each P or K set also select IDss for 250 mw dissipation max per device - use 2 or 3 or 4 devices in parallel. Yes this only works if you have a nice box of hundreds of P and K jfets to make up matched triplets or quads if you squirreled away enough 74/170's for future projects before they they were discontinued .......(Maybe Santa Nelson will donate the beast with a 1000 jfets for parts if you ask nicely - while we are at it lets ask for a pair of the Xs 300 - if he says yes to the first, the second is easy) 
if only we weren't such greedy little boys..............
if only we weren't such greedy little boys..............
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