Attached is a schematic for a low-distortion unity gain buffer. I call it the "Firefly" because of the yellow-green GaP LED used as level shifter for the p-mos output fet. I miss fireflies out here on the US West coast - they were a part of my younger days growing up in Florida and Virginia.
At any rate, the first schematic is the circuit I'm actually using, with depletion mode fets employed as current sources to reduce parts count. A somewhat more complicated ( but equally functional) circuit could be constructed using alternate current sources.
At any rate, the first schematic is the circuit I'm actually using, with depletion mode fets employed as current sources to reduce parts count. A somewhat more complicated ( but equally functional) circuit could be constructed using alternate current sources.
Attachments
I used an alternate circuit for simulation, As I haven't yet been able to integrate the Supertex depletion mode device models into PSpice/Orcad. As you can see, the simulated distortion is pretty low due to the short-path/total feedback. Real measurements will follow when I have a chance to make them. I have the buffer in my home listening setup right now as part of a RIAA/line amp single- board preamp, and it sounds pretty transparent.
Attachments
If you do get them modeled, please shout. I spent quite a bit of time trying to understand basic ccs design. a single FET or FET cascode having big advantages, but very sensitive to the bandwidth of the FET. My suspicion, only that because I am no expert, is that the linearity of the ccs is just as important as its impedance. About three projects out is a simple buffer with alternative ccs topologies to hear for my self. Constantlly looking for better transistors.
In the case of a single lowish-gain stage fed back (the thread http://www.diyaudio.com/forums/analog-line-level/206532-if-you-dont-have-sit-fake.html is an example), the characteristics of the current source loading the drain are important (shunt capacitance is a big one). I found it important in the real-world implementation of the "fake SIT" to cascode the drain load current source to reduce the effect of shunt capacitance across the CCS.
In the case of this circuit, where there are two cascaded high-gain elements, the shunt capacitance of the drain load CCS may not be as important, and a single depletion mode FET may suffice. The input fet is cascoded in this case to reduce the amplified Miller capacitance rather than due to linearity considerations. Since all the loop gain is fed back, the drain excursion of the input fet is limited, so that the amplified Miller capacitance may not be a big concern.
In the case of this circuit, where there are two cascaded high-gain elements, the shunt capacitance of the drain load CCS may not be as important, and a single depletion mode FET may suffice. The input fet is cascoded in this case to reduce the amplified Miller capacitance rather than due to linearity considerations. Since all the loop gain is fed back, the drain excursion of the input fet is limited, so that the amplified Miller capacitance may not be a big concern.
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