Balanced buffers - analogue volume control

[cbuzz99]

Hi guys,
I'm putting together a volume control for a balanced line source using a solid state IC. I'm not overly experienced with op-amps let alone in a balanced situation so I'd like a kick in the right direction.

The chips I am using (Cirrus CS3318) can cope with a maximum one-way peak of 9 volts. Would I be right in saying a +24dBu reference signal would peak at nearly 18 volts, so would require attenuating by a factor of two before entering the chip, then gained by a factor of two on the output as well?

I have seen a few different ways of buffering a balanced signal, what are people's opinions on setting up a buffer stage to handle balanced signals?

Lastly, and a bit noobish at that, the CS3318 has individual analogue reference pins for each input and output. Would it be possible to reference against one side of the balanced signal? Or would I need to use two control channels per balanced pair?

Thanks for any advice.

[sgrossklass]

Originally Posted by cbuzz99

The chips I am using (Cirrus CS3318) can cope with a maximum one-way peak of 9 volts. Would I be right in saying a +24dBu reference signal would peak at nearly 18 volts, so would require attenuating by a factor of two before entering the chip, then gained by a factor of two on the output as well?

Pretty much so, yeah. Note that section 5.2.1 of the datasheet says,

Signals approaching the analog supply voltages may be applied to the analog input pins if the internal attenuator limits the output signal to within 1.35 V of the analog supply rails.

Input amplitude can get to within 0.3 V of VA+/-, so the part is rail-rail input but not rail-rail output capable. You'll need a hair more than 6 dB (about 7.1 dB) if you really need +24 dBu output.

Note that unbal/bal conversion typically already gives you +6 dB.

Originally Posted by cbuzz99

I have seen a few different ways of buffering a balanced signal, what are people's opinions on setting up a buffer stage to handle balanced signals?

That would depend on your space, budget and performance constraints, obviously.
A basic 1-opamp line receiver is shown here. Then there's the 3-opamp instrumentation amplifier circuit, which you can also buy as a monolithic balanced line receiver IC for best CMRR. Some of these also come in gains of -6 dB, which would be ideal here.

You may want to poke your nose into Douglas Self's Small-Signal Audio Design book.

Originally Posted by cbuzz99

Lastly, and a bit noobish at that, the CS3318 has individual analogue reference pins for each input and output. Would it be possible to reference against one side of the balanced signal? Or would I need to use two control channels per balanced pair?

I think you could actually do the latter for improved dynamic range, though CMRR may not be all that great depending on how well gain is matched between channels. Normally you'd do something like this entirely single-ended, with balanced line receivers and transmitters at the ends.

[cbuzz99]

Performance is pretty much paramount - OPA series op amps are on the cards to give you an idea.

So far I've basically just considered a voltage divider and then a buffer stage going into the CS chip - running both balanced lines through the chip, then a gain stage on the output, but it seems messy to me, especially the resistances in the voltage divider for appropriate input impedance.

The CS chips are gain matched to +/- 0.1dB between channels and -120dB crosstalk.

I suppose if I run a line reciever on one end and a driver on the other, I'm not going to face any performance issues compared to attenuating and buffering the signal as balanced anyway.

[cbuzz99]

Bumpskis - anyone else willing to help out?