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Old 17th December 2010, 11:50 AM   #11
Macleod is offline Macleod  France
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Thank you. Will investigate that during next meeting this afternoon.
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Old 17th December 2010, 11:56 AM   #12
AndrewT is online now AndrewT  Scotland
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Quote:
Originally Posted by Macleod View Post
I got it. I matched jfet with same temp and same id, then same vgs.

Possible without matching by hand..?
this is not quite right.
The definition of Idss is that Vgs = 0volts and Vds = 10Volts and Tj= 25degC, then the current that flows is Idss.

Now turn that definition around and apply a Vds = 10Volts, pass an Id exactly equal to that device's Idss and provided Tj = 25degC then Vgs will be zero volts.

That's the beauty of the B1.
Pick two jFETs with the same Idss.
Use one as a Constant Current Sink (CCS).
The CCS will allow the follower to pass Id=Idss. Then Vgs of the follower is 0volts.

When Vgs is 0volts, that tells you and I that the voltage at the gate is exactly the same as the voltage at the Source.
Apply 0Vac to the Gate and the output, at the Source, is 0Vac
Apply 102mVdc to the Gate and the output is 102mVdc.
Apply 1Vac to the Gate and the output is 1Vac.

In other words the CCS loaded jFET acts as a unity gain follower/buffer.
But as with any Follower/buffer the current at the input is not the same as the current at the output. In general Buffers use tiny input current to generate large output current, they are current amplifiers.
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Old 17th December 2010, 12:10 PM   #13
Macleod is offline Macleod  France
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Ok for definition of Idss (I don't use often the equation, I work mainly with bjt).

But if we work the current source with vgs<>0, this vgs will also be the offset of the buffer no? (because upper fet will need same vgs for same Id)?

Idss and vgs=0 are not only a specific case to have zero offset?

Is vgs=0 required even if DC offset is of no importance? (wonder why it is used on B1 with 2 coupling cap)
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Old 17th December 2010, 05:07 PM   #14
AndrewT is online now AndrewT  Scotland
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The B1 uses a single supply.
It uses, as do all amps that run at elevated voltages, capacitors to block DC and allow AC signals to pass.

The DCB1 uses a dual polarity supply and relies on the follower running at Idss for it's IC to generate no DC output offset of it's own.
It run at voltages around the signal return voltage and thus does not need DC blocking caps to operate.

Because the DCB1 is DC coupled it will pass DC from a Source to a Receiver.
The B1 is AC coupled.
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Old 17th December 2010, 05:08 PM   #15
AndrewT is online now AndrewT  Scotland
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Quote:
Originally Posted by Macleod View Post
But if we work the current source with vgs<>0, this vgs will also be the offset of the buffer no? (because upper fet will need same vgs for same Id)?
I don't understand what you are trying to tell/ask us.
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Old 21st December 2010, 07:41 AM   #16
Calvin is offline Calvin  Germany
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Hi,

when You use matched JFETs and sysmmetrical power supplies, give the sourcefollower-JFET the same source resistance as the currentsource-JFET and the offset will be 0. In any different case the offset will be off of 0.
Because of the gm not beeing infinite, the gain of the follower will be less than 1 (>0.9), with lower gm-values resulting in lower values.
You may also think about cascading high-gm/low-Ugs JFETs with lower-gm/high-Ugs devices to achieve a gain very closely to 1, to get a low output impedance value, to deal with heat-/power-problems and to avoid Udg possibly becoming too high.
The reason for running the JFETs at Idss is that Idss is the maximum current a single-ended ccs-loaded circuit running in class-A can provide into the load. But if Your load current requirements are modest it might be advantageous to use source resistors and run the JFET on a lower-than-Idss current value and enjoy the less stringent requirement for matching tolerance. Alternatively You could modify the constant current source into a voltage controlled current source, which would allow for higher-than-Idss currents into the load.

jauu
Calvin

Last edited by Calvin; 21st December 2010 at 07:52 AM.
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Old 27th December 2010, 12:31 PM   #17
Macleod is offline Macleod  France
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Thank you for your advises.

Last week, before going holidays, I tried to simulate all that in a first try. I am almost satisfied of the results of this.

To summurize :

Differential output :
- THD20 20Vpp : 0.0022%
- THD20 4Vpp : 0.000082%
- THD20 1Vpp : 0.000005%
Differential buffer output
- THD20 20Vpp : 0.002067%
- THD20 4Vpp : 0.000075%
- THD20 1Vpp : 0.000005%

I didn't have time to optimize the circuit to improve non-differential performances, it seems different values must be used if we need differential use or not.

Some comments on the schematic :
- I draw it as a super-symetric-differential-buffer just for artistic reasons. Find the part that are not differentials...
- +/-24V is used to allow high ouput swing and rather good linearity with resistors replacing current sources.
- Q19, Q20 are input buffers. I didn't use Jfet as I don't really mind about offset (and as I think any BJT is already matched for this application compared to JFET), the differential buffer will remove it. I just need a good buffer and gm of BJT may do the job.
- Q21, Q22 are the emiter source current for input buffer. Need to be optimized for high input level and low load resistors (Ra, Rb)
- Q17, Q18 is the differential pair of the previous schematic posted. Current source has been removed to simplify and replaced by R26
- Q15, Q16 is the cascode pair of previous schematic. Current sources have been replaced by R24, R25 to simplify. Base voltage is controled by Q1 to eliminate output offset (more on this later)
- Q14, Q13 is output buffer, R20, R21 are low to allow high swing in low ouput impedance (10Vpp on 1k is ok) (have to think about power dissipation for Q13, Q14)
- Q1, Q2 is a differetial pair that controls ouput offset. Voltage is sensed using R34, R35.
- C5, C6 have not been optimized (did no loop gain/phase simulation). First try values as a guess.
- I just played with available components in standard versions.
- Playing with temperature didn't help to optimize ouput offset, it stays to -27mV due to matched models...


This is all I will provide today, I am back to work and have to do some job...

I hope my first circuit contribution to DIYaudio will be received indulgently.


Any comment welcome! (on schematic or LTspice use...)
Attached Files
File Type: zip DiffAmpBuff v8.zip (2.2 KB, 60 views)
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Old 27th December 2010, 12:36 PM   #18
Macleod is offline Macleod  France
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Quote:
Originally Posted by AndrewT View Post
I don't understand what you are trying to tell/ask us.
I proposed to run Jfets at lower Id than Idss. For this, Vgs will need to be modified (Vgs<>0) and then offset appear.
As Calvin said, no real added value, maximum current is best for buffer.

The idea behind this was not to use Jfet running with Vgs=0, but using BJT with Vbe=0.7V. The end of the idea is the schematic posted above. As you see on schemtic, I can manage input buffer offset in another way.
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Old 28th December 2010, 09:50 AM   #19
Macleod is offline Macleod  France
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Maybe something wrong with my previous messages?
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Old 28th December 2010, 11:24 AM   #20
AndrewT is online now AndrewT  Scotland
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Hi,
Now I understand.
Most jFETs are biased to between 50% and 90% of their Idss.
Some are biased much lower than this.
I only know of the B1 that is biased to 100%.

You and many others have tried biasing a jFET at other than Idss. The results are usually satisfactory.
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