Salas hotrodded blue DCB1 build

[wendell c]

Ok, been stuffing the boards with parts I have available. If we are looking at the board horizontally on top right IRFP240 it looks as if there is an insertion hole missing for one end of the 470r resistor.

Also, the BOM states that there are 4 sk170 matched, where on the board do they go?

[Macronaut]

Originally Posted by wendell c

Ok, been stuffing the boards with parts I have available. If we are looking at the board horizontally on top right IRFP240 it looks as if there is an insertion hole missing for one end of the 470r resistor.

Also, the BOM states that there are 4 sk170 matched, where on the board do they go?

Concerning that 470R resistor, the pad is there. However, it is positioned on its end instead of mounting flat against the board. This was done as a compromise for the board layout.

The matched 2SK170's are in a row near the muting relay marked 4x 2SK170BL. You will want to keep the the matched FET's together with one set on each side. They are arranged so one set will have the flat side pointing to one side and the other set reversed from that. I believe that if you have a set of FET's where one has a slightly higher Ids than the other (eg. 7.7 & 7.8 Ids) then you place the higher Ids (7.8) in the middle of that row. The signal FET (7.7) is on the end of the row.

[AndrewT]

Originally Posted by Macronaut

I believe that if you have a set of FET's where one has a slightly higher Ids than the other (eg. 7.7 & 7.8 Ids) then you place the higher Ids (7.8) in the middle of that row. The signal FET (7.7) is on the end of the row.

there was an earlier poster who claimed that he got better sound by running the amplifying FET at a bias above it's Idss.

I disagreed then and still do now.
A jFET follower will tolerate some higher current running during signal induced high Vgs, read Curl. But there is a big downside to using a high bias at above Idss and then applying the signal induced Vgs sending current even higher.

I would much rather run the bias at 95% of Idss rather than set bias to 105% of Idss
What the B1, as proposed by Pass, does is run the FET follower at very near but not above 100% Idss.

[Salas]

Originally Posted by wendell c

Also, the BOM states that there are 4 sk170 matched, where on the board do they go?

Middle ones are to be the (very slightly) lower IDSS ones between matched pairs. Example.

Please make all assembly questions to the building thread so we keep them together in a known place.

P.S. The new board & its circuit we talk about for people bumping here to understand, are in the pictures below:

[AndrewT]

Hi Builders,
place your solutions and problems here.

[ppcblaster]

Originally Posted by AndrewT

Hi Builders,
place your solutions and problems here.

[Salas]

OK, I moved the relevant posts here, although they went to the top because they auto arrange in chronological order. Is it OK?

What was that you wanted to know ppcb?

[dvb-projekt]

Started a GB for the new Mundorf HighEnd M-LYTIC AG psu caps

[ppcblaster]

Here is my BOM please advise.

[Salas]

To understand, your question is about opinions in parts quality decisions? If yes, the members will surely have comments.

*Here I upload the general BOM guide too so it can be found in this thread as well.