15 and 20dB is times 5.6 and times 10. So not that high offset multiplication. GC is 1+(Rf/Rfi). If it is something like 22K from output to other input and 220R to ground, then its 101 times or ~40dB. That one can take it to -450 mV. Not sure it may be a real problem still or if it even offsets some already positive amp's own. If you will make a mutual swap between the two audio section ''matched'' JFETs on your -4.5mV DCB1 channel, it can score lower if lucky. Or higher if unlucky.
the -ve output offset (if you measured correctly) indicates that the Vgs is -ve. That tells you the Id is less than Idss.
You achieve this by using the lower Idss device for the CCS and the higher Idss device for the Follower.
BUT. You cannot measure the Idss accurately enough to ensure that two almost identical devices are the correct way around. The "test" is to measure the actual operating conditions and identify the -ve offset at the output.
There was one Member that reported inserting them the wrong way around gave better sound quality.
I cannot recall any corroboration.
Looks like you have not read the Thread.
You achieve this by using the lower Idss device for the CCS and the higher Idss device for the Follower.
BUT. You cannot measure the Idss accurately enough to ensure that two almost identical devices are the correct way around. The "test" is to measure the actual operating conditions and identify the -ve offset at the output.
There was one Member that reported inserting them the wrong way around gave better sound quality.
I cannot recall any corroboration.
Looks like you have not read the Thread.
John Curl had given his approach on this once: http://www.diyaudio.com/forums/solid-state/120243-variation-jc-2-preamplifier-5.html#post1471389
JC is referring to the DC bias being less than Idss.
And takes us through the story explaining that the AC (signal) allows +ve Vgs on the alternate half cycles.
I read that as meaning that DC bias should not be set to greater than Idss and that short term signal excursions into the Id>Idss are allowed. The B1 and the DCB1 are exactly that Id=Idss and signal produces +ve Vgs on alternate half cycles.
There is a proviso mentioned elsewhere. Be careful with high Id >Idss and gate leakage, particularly if Vds & Tj are also high.
As an aside, Tj will be high, if Id bias >= Idss and Vds is high as in a follower.
And takes us through the story explaining that the AC (signal) allows +ve Vgs on the alternate half cycles.
I read that as meaning that DC bias should not be set to greater than Idss and that short term signal excursions into the Id>Idss are allowed. The B1 and the DCB1 are exactly that Id=Idss and signal produces +ve Vgs on alternate half cycles.
There is a proviso mentioned elsewhere. Be careful with high Id >Idss and gate leakage, particularly if Vds & Tj are also high.
As an aside, Tj will be high, if Id bias >= Idss and Vds is high as in a follower.
See if your diodes are populated in the right orientation following the printed stripes for cathode on pcb, see if any one of them is charred also. Disconnect the trafo and see with the meter in ACV mode that the wires you sent to the outer terminals of the AC in pcb connector are the expected secondary sum value. Also that each one measures half that in respect to the wire(s) you sent to connector's middle point.
Square hole is Led's anode in this pcb as crt designated that half circle symbol over the 5 Led groups, when its the cathode in the 3 Led groups. If you put just one in reverse they will not shine, but no reason to blow a reservoir cap. In fact its the first time I hear someone blows a reservoir cap. Could it be it was reversed for polarity by accidental insertion or just very unlucky to chance on a dodgy one?