John Curl's Blowtorch preamplifier part II

[Juergen Knoop]

I'm not overly obsessed with averaged noise measurements, but I'm curios about peaks that might feed through into the audio signal.
Is this a non-issue in high-end audio?
Presumably there is no DIY solution for a quasi-peak meter available?
Regards

[ikoflexer]

Ah, thank you, it was me indeed! It's the bad way I expressed myself again. What I really meant was that I didn't see one with output impedance that is flat across, with no peaks above 1 milliohm, all the way to 10MHz.

Here's a plot I used a while ago when comparing to some popular regulator: lhs plot is the popular regulator, rhs plot shows what I was trying to say and failed. Obviously, we're in the fairy land of simulators here.

[dimitri]

As you see, the output impedance peaks at 5milliOhm at around 1MHz

Is this a simulation of the circuit on the left, or the circuit with parasitics (output cap L, ESR, etc)?

[syn08]

Originally Posted by dimitri

Is this a simulation of the circuit on the left, or the circuit with parasitics (output cap L, ESR, etc)?

Yes, no parasitics considered. Simulation I was asked, simulation I provided. As I said, I have no means to directly measure the output impedance. My estimate is around 10milliohm (in the MHz range), with SMD parts and force/sense wiring.

BTW, your estimate of parasitic reactances you posted a few pages up was 3 orders of magnitude off.

[dimitri]

BTW, your estimate of parasitic reactances you posted a few pages up was 3 orders of magnitude off.

I know, I'm in a hurry and I edited my post:

Yes, syn08, I omit 10^-3

[syn08]

Originally Posted by ikoflexer

Ah, thank you, it was me indeed! It's the bad way I expressed myself again. What I really meant was that I didn't see one with output impedance that is flat across, with no peaks above 1 milliohm, all the way to 10MHz.

That's an easy one. Just play with the gate resistor and, while you cannot cancel the peak (a pole is a pole, and is certainly a pole ), you can easily bring it under 1milliohm. Depending on the MOSFET type, try around 300ohm.

[Steve Dunlap]

So hang on there Steve. Your mind is alive and you think clearly.

There are some here that disagree with that.

[john curl]

Well, everyone, I am from the 'old school' of designers, as you well know.
This reminds me of a situation that I had at Cal Berkeley, while waiting for an engineering class to begin. I was in the 'canteen' having a cup of coffee, when some fellow students who attended my class were discussing an engineering problem at the next table. Our professor had previously assigned some homework vaguely similar to what Syn08 is appearing to be telling me that I am missing out on. It was mathematically elegant, sophisticated, yet the student worrying over the problem could not figure out what a factor of 10 was in the middle of the set of equations.
I glanced over and pointed out that the factor of 10 was Gm Rl or the voltage gain of the fet stage that we were analyzing. Yes, the point of the exercise had been completely obscured by the math. Such is a university education, sometimes. However, I was not merely a student, at the time. I had 5 years experience as a designer in an engineering firm, under my belt, before I took this course. I learned my design rules from other engineers, on the office.
I could see the problem from inspection, and a slide rule. It is the same here. Gm Rl = the gain of the noise More Rl, more noise. More Gm, more
noise. Super high Idss gets you medium Gm, VERY LOW R = less noise
However, low Gm, and medium Idss allows LOW R and LOW Gm times LOW R gives a good result also. It must be remembered that Gm FOR A GIVEN DEVICE GEOMETRY changes as the square root of the Idss, but the Rl DROPS in value directly with Idss. Therefore, there is an advantage in using higher Idss WITH THE SAME DEVICE GEOMETRY, in this design example.

[syn08]

Originally Posted by john curl

Well, everyone, I am from the 'old school' of designers, as you well know.
This reminds me of a situation that I had at Cal Berkeley, while waiting for an engineering class to begin. I was in the 'canteen' having a cup of coffee, when some fellow students who attended my class were discussing an engineering problem at the next table. Our professor had previously assigned some homework vaguely similar to what Syn08 is appearing to be telling me that I am missing out on. It was mathematically elegant, sophisticated, yet the student worrying over the problem could not figure out what a factor of 10 was in the middle of the set of equations.
I glanced over and pointed out that the factor of 10 was Gm Rl or the voltage gain of the fet stage that we were analyzing. Yes, the point of the exercise had been completely obscured by the math. Such is a university education, sometimes. However, I was not merely a student, at the time. I had 5 years experience as a designer in an engineering firm, under my belt, before I took this course. I learned my design rules from other engineers, on the office.
I could see the problem from inspection, and a slide rule. It is the same here. Gm Rl = the gain of the noise More Rl, more noise. More Gm, more
noise. Super high Idss gets you medium Gm, VERY LOW R = less noise
However, low Gm, and medium Idss allows LOW R and LOW Gm times LOW R gives a good result also. It must be remembered that Gm FOR A GIVEN DEVICE GEOMETRY changes as the square root of the Idss, but the Rl DROPS in value directly with Idss. Therefore, there is an advantage in using higher Idss WITH THE SAME DEVICE GEOMETRY, in this design example.

I couldn't put it in a more complicated/confusing language, but slowly, slowly is going there

[john curl]

It must be again pointed out that some jfet geometries, have more Gm@Id than others. The reason for this is related to the geometry, for example LONG GATE devices tend to have lower Gm@Id, while SHORT GATE devices have higher Gm@Id.
Also, all jfet geometries have higher Gm:Id ratio when operating at lower currents, in this case Idss. Therefore, a higher Idss part has a lower Gm:Id ratio and this justifies a smaller Rl as well, so the total noise gain is less than a lower Idss part.
So for a GIVEN Idss, the long gates will tend to perform better as a current source, since they won't amplify their own noise as much, and higher Idss long gate devices will be quieter in this case, as well.
Now comes the hard part, what is the intrinsic noise of the jfet under consideration? This is where data books, Quantech Noise Analyzers, or their equivalent, experience, and a little Van der Ziel comes in handy.
It so happens that the base noise of a jfet is approximately: R(noise) = 2/3 times 1/Gm. For example: the base noise of a 4000 mS fet at 6ma,(2SK246) might be 250 times 2/3 = 170 ohms or about 1.7 nV/rt Hz. You won't get better than this with this Gm in a fet at room temperature and above.
Now look at a 2SK170: Gm at 6ma is: 33,000 mS, 20 ohms noise eq. Big difference! and the noise could possibly be as low as 0.58nV/rt Hz Pretty darn good, about 1/3 the noise of the 2SK246. However, with the SAME Rl, the 2SK170 will measure worse, just like Syn08 measured. This is because the Gm of the K170 is 8.2 times greater than the K246. Noise times Gm times Rl =?
Please, those who can, do the math, yourself.
Also, please understand that LOW NOISE JFETS are not just any fet. They are processed for minimum 1/f noise at audio frequencies. Many jfets will not work very well because they were made more cheaply, perhaps as a switch, and can have a lot of excess noise.