Unfortunately no, part of the reason is the input signal has to be reduced in view of the doubling of the gain. The compensation can be done another way which ignores changes of phase in the output stage by taking the feed from the collector to the inverting input.
Only one capacitor is needed since both circuit halves are coupled by a large capacitor the single capacitor C3 is shown in the screen shot in a new position and C35 which is out of view deleted.
Reduce the test signal to 0.2V and try the tests again. There is something wrong with the set up you are using - look back at earlier posts and copy the settings down.
The Bode plot and square wave tests will have to be re-run. I have simulated a simplified version of this circuit with the same compensation method.
In this case that will have to wait for another day.
Only one capacitor is needed since both circuit halves are coupled by a large capacitor the single capacitor C3 is shown in the screen shot in a new position and C35 which is out of view deleted.
Reduce the test signal to 0.2V and try the tests again. There is something wrong with the set up you are using - look back at earlier posts and copy the settings down.
The Bode plot and square wave tests will have to be re-run. I have simulated a simplified version of this circuit with the same compensation method.
In this case that will have to wait for another day.
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You have made other changes than these. I changed the circuit compensation and have now checked the 1kHz THD. The result is not the sort you have been hoping for.
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I have little better results, 0.04% THD on 20KHz region with high capacitance on out. The main problem seem to be in the input stage. If you lower the input voltage amplitude the THD will decrease proportionally even more. Somehow instead of unify a hot and cold signals, the circuit amplifies them separately and doubles the gain which produce distortion I guess.
Also we can try and compare Ian's Rush pairs input stage. Do you know how to implement it? Or maybe Ian will generously make it.
Also we can try and compare Ian's Rush pairs input stage. Do you know how to implement it? Or maybe Ian will generously make it.
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The title of this thread should be of interest to those aspiring to design. However it serves no purpose if random amendments are made without any tracking and a proper explanation behind the changes in behavior that occur. The first thing to establish is, what stability parameters are you working to?
While this is an accurate statement for the schematic as drawn, it does not evaluate a range of conditions.
In my view, a design needs to be evaluated progressively:
1. Open loop behavior.
2. Stable operation with no load.
3. Stable operation with resistive load.
4. Stable operation with resistive load and parallel capacitor.
5. Distortion performance.
6. Stable power up without squealing.
The cycles of development will require undoing of previous changes because, paraphrasing Kirchhoff, 'everything affects everything else'.
You don't need to consider the Zobel until the end in my view. This design has potential and will require 2 - 3 weeks of simulator work to optimise. However, no one will learn anything unless a logical engineering approach is adopted.
While this is an accurate statement for the schematic as drawn, it does not evaluate a range of conditions.
In my view, a design needs to be evaluated progressively:
1. Open loop behavior.
2. Stable operation with no load.
3. Stable operation with resistive load.
4. Stable operation with resistive load and parallel capacitor.
5. Distortion performance.
6. Stable power up without squealing.
The cycles of development will require undoing of previous changes because, paraphrasing Kirchhoff, 'everything affects everything else'.
You don't need to consider the Zobel until the end in my view. This design has potential and will require 2 - 3 weeks of simulator work to optimise. However, no one will learn anything unless a logical engineering approach is adopted.
The closed loop behavior is governed by two feedback paths via R19 and R20. If these paths can be broken, then one can begin to observe the open loop behavior. Component changes in the open loop environment will yield more dramatic changes than the closed loop one. This will give you an insight into the key elements that drive stability.
The Tian probe is a sophisticated method for open loop, however there is the cheat method. Place a high value inductor (100H) in series with the output feedback to R19 and R20, and a 10000mF capacitor to ground, which effectively removes all AC components from the feedback. LTspice doesn't seem to understand Farads.
Now you can see the effect of compensation capacitor adjustments on the open loop bandwidth. The gain available at 10KHz will change enormously.
The Tian probe is a sophisticated method for open loop, however there is the cheat method. Place a high value inductor (100H) in series with the output feedback to R19 and R20, and a 10000mF capacitor to ground, which effectively removes all AC components from the feedback. LTspice doesn't seem to understand Farads.
Now you can see the effect of compensation capacitor adjustments on the open loop bandwidth. The gain available at 10KHz will change enormously.
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If you are putting your hand up for this task that is very generous of you. The originator is already thinking about a change of direction with the input stage.
I don't see there is ever going to be any satisfaction here and the quicker I can move on the better.
Well if the objectives have changed I can leave you to it. In my view the stability investigation amounts to scratching the surface. The design is viable, with the proviso that the differential input does not function as a differential input, as Mjona originally observed. If you want easy gratification go with what you have and I won't bother improving the design.
Hi Andriy,
What title would you like for this thread. The moderating team can change it for you.
-Chris
Don't you think that this is asking a lot from members who are trying to help you? I think that the onus should be with you to do the investigations, and it seems that you need more practice with the simulator. It's not proper form to challenge someone's advice given freely to assist you with your problem.
What title would you like for this thread. The moderating team can change it for you.
-Chris
Hi Chris,
I didn't ask Spladski, only wrote the new design ideas are welcomed. Everyone has a right to post here their thoughts or not, I think (didn't read the policy actually, sorry). From my side I will do everything required what I can. Yeas, you are right, my practice with Spice started with this thread. I'm very sorry if someone got insulted with my previous post, my intentions were completely different.
Thank you for your kind offer Chris! I think it would be best to rename the thread as Ian called this amp design a couple of pages ago: "One of the Top DiyAudio Solid-State CFA amp design".
Btw, it's not for me only, I would very like it could be available for everyone who wish to build it. I'll make a layout and publish it here when the amp will be ready.
Best Regards,
Andriy.
I didn't ask Spladski, only wrote the new design ideas are welcomed. Everyone has a right to post here their thoughts or not, I think (didn't read the policy actually, sorry). From my side I will do everything required what I can. Yeas, you are right, my practice with Spice started with this thread. I'm very sorry if someone got insulted with my previous post, my intentions were completely different.
Thank you for your kind offer Chris! I think it would be best to rename the thread as Ian called this amp design a couple of pages ago: "One of the Top DiyAudio Solid-State CFA amp design".
Btw, it's not for me only, I would very like it could be available for everyone who wish to build it. I'll make a layout and publish it here when the amp will be ready.
Best Regards,
Andriy.
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Attached is mjona's last circuit now modified with a Rush differential input stage and re-biased for similar idle current and VAS current.
The THD results at 1kHz 0.1ppm, and 20kHz 2ppm both at 30Vpk into 8 ohms
That's a good start! I hope you can get close to this with a real amp.
I have not changed the compensation capacitors, only the input stage and biasing.
BTW C23,C26 have been disabled since they are not needed, assuming the 60V rails will well filtered by the power supply for these rails.
I don't recommend C20 across R21 since cross-conduction can occur as my sims showed (Post #313) but I haven't changed that either. Also, I'd recommend emitter degeneration of the CFP drivers Q18,Q19, eg Post #280.
Stability needs to be checked into the range of capacitance's (as previously simulated), as well as clipping recovery. A single compensation capacitor (as suggested by mjona) since there may be an issue with clip recovery with two compensation caps (eg check for power stage cross-conduction when clipping and driven with say a 20kHz squarewave).
I'd like to leave these and any further changes to yourself or anyone you prefer. Otherwise I am available to help finalize this amp. All the best.
Cheers,
Ian
Since this thread is supposed to be educative for inexperienced designer apprentices, would any charitable soul kindly post a screen shot of the interesting part of the Bode plot that confirms stability of the circuit?
I imagine circuit must be stable before adding Zobel, right?
Thanks for your patience and constant advice and support.
M.
Eternal beginner.
Anyone tried to sim with square wave input? Is it possible to use it as SE?
Thank you for the schematic Ian!
Without Zobel, with 2uF load
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Squarewave sims
Pleased to help, pleased it works, pleased it works so well.
Re SE you can either ground the inverting input OR se the sender inverter gain (E1 bottom LH corner) to zero. It is normally -1 for inverting. This inverter simulates the sending end for a balanced input signal for the amp.
Re squarewave input.
There is a problem with LTspice (inherited from the original SPICE) that the squarewave does not start from 0V which is needed in amplifier .trans simulations to establish the correct steady state dc operating point.
You have to make your own PWL but this is only practical for 2 cycles. A post by 'Tibouchina' here Current-Source-Driven-power-transistors-and-mitigating-cross-conduction-distortion gaves a way to make a 1 cycle PWL repeat as long as you want using
Tramp is useful for limiting the rise time of the squarewave to avoid unwanted slew limiting of the early stages. It does what the input filter does (the input filter has not been added to your circuit yet). Set it to say 1u for this amp, that's around 100V/us with a near full swing output.
Good to see your AC plot. Nice going.
Pleased to help, pleased it works, pleased it works so well.
Re SE you can either ground the inverting input OR se the sender inverter gain (E1 bottom LH corner) to zero. It is normally -1 for inverting. This inverter simulates the sending end for a balanced input signal for the amp.
Re squarewave input.
There is a problem with LTspice (inherited from the original SPICE) that the squarewave does not start from 0V which is needed in amplifier .trans simulations to establish the correct steady state dc operating point.
You have to make your own PWL but this is only practical for 2 cycles. A post by 'Tibouchina' here Current-Source-Driven-power-transistors-and-mitigating-cross-conduction-distortion gaves a way to make a 1 cycle PWL repeat as long as you want using
where tramp is the rise time from -Vpk to Vpk and f is the frequency (1/T or 1/Period) so these 3 parameters need to be defined using .param statements. I don't have time now to set this up and attach it but can later if you get stuck. Tip: You can enter the command line above from the clipboard (to save typos) by opening the sine wave text line itself (not the advanced setting box) and (delete) paste over the existing "SINE(0 {Cin} 1k)", then enter.
Tramp is useful for limiting the rise time of the squarewave to avoid unwanted slew limiting of the early stages. It does what the input filter does (the input filter has not been added to your circuit yet). Set it to say 1u for this amp, that's around 100V/us with a near full swing output.
Good to see your AC plot. Nice going.
An off topic question if you don't mind.
What is the distortion percent in the parenthesis. I see some dot four in LTspice sims which only have one result. What is the second and how does one control whether there is one or two results?
Cheers.