I think we need to be a little more specific when we say close to zero THD.
Here's a suggested starting point for a 100W BJT power amplifier with 2 output pair driving 8 ohms at any power level up to full power. THD-1 less than 0.0005%, THD-20 less than 0.003%.
Cheers,
Bob
Scott
It would be cool to see you design a 100W power amplifier with those specs, rock stable into any load.
Reodor
The power output has little to do with it, the limited ft of power devices requires a strategy for lowering the GBW. Emitter degeneration is the easiest so now there is a positive noise gain from the current mirrors to the input. I don't see the point of a 1nV PA, increasing the open loop linear transfer function at the expense of noise is far more valuable.
I suspect you might mean, lowering the GBW without reducing the slew rate too much.
If reduced slew rate is acceptable, you could just increase the compensation capacitor. To prevent big Ccomp from creating a right half plane zero, you could install a good old Yannis Tsividis x1 buffer between VAS collector and Ccomp.
_
Attachments
Simply putting a small resistor in series with Ccomp also eliminates the zero. The value of the resistor should be 1/gm of the degenerated VAS. A value larger than that can be used for Rseries, in which case it will introduce a LHP zero that will provide a little bit of phase lead compared to the theoretical 90 degrees of lag that the Miller compensation provides.
Cheers,
Bob
It all goes together increasing Ccomp increases the input error signal making THD worse while preserving the noise performance which is essentially useless.
I'm unaware of any VAS stability issue that is introduced when adding the resistor, as long as its value is not excessive. Bear in mind that its value for canceling the zero will be on the order of the value of the VAS degeneration resistor value, often in the neighborhood of 22 ohms. Note that in a typical case where the Miller cap is 30pF, the zero that would normally be introduced is pretty high in frequency.
Cheers,
Bob
http://web.mit.edu/klund/www/papers/ACC04_opcomp.pdf discusses added series R for a zero in Cdom (~ halfway thru)
Hi Bob,
hi jcx,
probably, the remark was not clear enough. It concerned the creation of an additional zero for the main loop.
I'm refering to p. 176/177 of Bob's book and did not remember the last sentence "Caution must be exercised with this technique to avoid compromising gain margin". (It is, however, not clear for me whether this relates to global loop or minor VAS loop.)
The problem is described around Figure 37 in the reference from jcx. Maybe, one can also combine the solution with high-frequency shunting of the VAS emitter degeneration. Anyway, one should consider the issue when trying to mitigate influence of a main-loop pole with the additional resistor.
Thank you for the reference, jcx. (If I remember right, you already have introduced it, some time ago.)
Cheers,
Matthias
Edit: All depends, of course, on values. Assuming the 5MHz pole example from the book, and an attempt to mitigate it with an additional main-loop zero at 10MHz, then this additional pole in minor VAS loop may be in dangerous vicinity of original crossover frequency in minor VAS loop.
Last edited:
That's a good paper jcx provided. Bear in mind that the author was introducing a zero at a frequency below the ULGF to compensate for a heavy pole created by the capacitive loading. The need for a high enough resistance in series with the compensating capacitance in order to insert a zero at such a relatively low frequency is what led to the minor loop instability. Inserting a small resistor to cancel a RHP zero created by the Miller capacitor has its effect at a much much higher frequency, and involves the insertion of a much, much smaller resistance.
Cheers,
Bob
The feed-through zero is out of question. For the main-loop zero, one should also remember that crossover frequency in our VAS is probably lower than that in the op amp example.
Finally, all depends on the phase margin one would like to maintain in the minor VAS loop; a bit a question of taste. Some people only consider it a problem, if peaking in main loop occurs.
Cheers,
Matthias
Hi Bob
OK for me.
I'm just adding two decimals when I'm talking about "close to Zero THD"
Cheers
Reodor
Hi Scott
You don't get my point, I'm talking about very low noise and very, very low distortion.
So I'm not talking about lowering the open loop linear transfer function to get lower noise.
Reodor
I'm not either, I'm not sure what the above is supposed to mean. The point about the noise is that there is no source with noise at its output even remotely at the nV level more likely 20-100nV at best, 50 Ohm volume controls are not common.
Last edited:
THD-20 is really where it is at. Very low THD-1 is fairly easy to achieve. If you are suggesting that you can achieve 0.00003% THD-20 at any power up to full power into 8 ohms with a BJT output stage without error correction, my hat goes off to you. Tell us how you did it.
Cheers,
Bob
Hi Bob
That is a splendid idea.
In your opinion I should actually give away some years of thinking "free of charge"
(not that I have been thinking about it all the time, but it has been there in the back of my head all the time). It is not easy to achieve the THD and Noise numbers that I actually do.
What do you think will happend if I'm posting the circuit?
The answer is quite simple:
- I will spend the next few years, explaining how the circuit works. Not only to the DIY people, but also to the Audio industry all over the world.
- "DiyAudio" will actually own the circuit (that is the "Rules") and can do whathever they like to do with it.
- Some will write articles about the circuit and some will include it in a book claiming that they came up with something smart.
So thank you for the splendid idea, but no thanks.
Cheers
Reodor
You sound like you are full of yourself.
What level of THD-20+N did you actually achieve?
Cheers,
Bob