Hi Mr. Cordell
I am working on single ended IPS with symmetrical VAS close to Fig. 7.16 of page 146 in your book. I see some potential saturation problem of the current mirror Q5 and Q6 due to mismatch of Q1 and Q2 or even Q5 and Q6. I want to run this by you because I saw others present similar circuit in their articles including Groner Fig. 56 in page 48. So I could be wrong.
I was worry about the high impedance of the CM on both side. Q7 and Q8 only set the general bias voltage of the high impedance notes of IPS. But it does not set the individual voltage of the collector of Q5 and Q6. I suspect when there is a mismatch of Q1 and Q2, one side of the current mirror that has more current can go into saturation.
D1 and D2 in Fig. 7.16 can prevent the saturation, but if one of the diode turns on, That presents a low impedance path between the two sides of the IPS. That definitely lower gain and more important, increase distortion as the impedance of the diode is logarithmic.
Attached is the two simulation circuit with LTspice. Even though it's BJT, but the effect of mismatch is the same. One without diodes and one with diodes. I change one differential transistor from 2N2222 to 2N4124. Notice in the circuit without diodes, one transistor of the CM is up to 38.8V. This is saturation. The circuit with diodes has about 0.4V difference in voltage, that is a sign that the diode is slightly turn on.
Can you comment on this?
Thanks
I am working on single ended IPS with symmetrical VAS close to Fig. 7.16 of page 146 in your book. I see some potential saturation problem of the current mirror Q5 and Q6 due to mismatch of Q1 and Q2 or even Q5 and Q6. I want to run this by you because I saw others present similar circuit in their articles including Groner Fig. 56 in page 48. So I could be wrong.
I was worry about the high impedance of the CM on both side. Q7 and Q8 only set the general bias voltage of the high impedance notes of IPS. But it does not set the individual voltage of the collector of Q5 and Q6. I suspect when there is a mismatch of Q1 and Q2, one side of the current mirror that has more current can go into saturation.
D1 and D2 in Fig. 7.16 can prevent the saturation, but if one of the diode turns on, That presents a low impedance path between the two sides of the IPS. That definitely lower gain and more important, increase distortion as the impedance of the diode is logarithmic.
Attached is the two simulation circuit with LTspice. Even though it's BJT, but the effect of mismatch is the same. One without diodes and one with diodes. I change one differential transistor from 2N2222 to 2N4124. Notice in the circuit without diodes, one transistor of the CM is up to 38.8V. This is saturation. The circuit with diodes has about 0.4V difference in voltage, that is a sign that the diode is slightly turn on.
Can you comment on this?
Thanks
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That circuit has just inspired a thread >HERE. "My first Amp..."<.
It motivated me to look more closely and I am a bit less convinced this time around.
However, it's a fun circuit to study and learn from, I'm sure the OP would welcome your comments.
Best wishes
David
I have some issues with his design. I read to Fig.5 and Fig.6 and I cannot go on.
1) He put so much stress on power supply rejection where in real life, just use resistor and a huge cap to smooth it out. I just cannot see putting in a 3rd stage to fold the cascode to ground reference. One extra stage is one extra source of distortion.
2) He never talked about the first folded cascode Q3 and Q4 is -ve power rail referenced. Also the current mirror Q5 and Q6 are +ve rail referenced. If there is noise on the rails, how does this circuit any better?
3) This is also true for Q11 and Q12 that they are rail referenced.
4) The Q7 and Q8 used has to have R5 and R6 reference to rail. Even if he uses CCS or whatever, how does that get away from the supply rails. If you count the number of points this circuit referencing to the supply rails, I am not sure the number is any less. NOT to mention about the distortion of the third stage introduced.
To everyone here:
Yes, I like the idea of single miller cap compensation. This is very valid, this is the very point that I am stuck since yesterday after I decided to go single ended IPS. I cannot get down to single compensation cap if I want symmetrical VAS. I still do not get a clear answer what's so wrong of single sided VAS with CCS on top. No body answer what if I up the current of the CCS to increase the slew rate. Who cares whether the slew rate is symmetrical if slew rate of both sides are much faster than required? If you can make the slower side to be at least 30V/uS, what do you care whether the other side can do 60V/uS? What's wrong to use 20mA CCS? If still worry, use 3EF OPS to up the input impedance.
Is supply ripples that important? there is build in PSRR in all these designs. If I am that anal about this, I WILL put in regulated supplies to up the rail voltages a little. Floating regulated 5V supply is common enough and easy enough to implement. I'll stick with 2 stages any time of the day.
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Hi Forr,
Neat circuit. Note that it is effectively a unipolar N-channel JFET input stage, what I like.
Also note it is really a four-stage amplifier; JFET LTP first stage, complementary "diamond" second stage, push-pull VAS third stage, Double EF output fourth stage.
Note also it is lag-lead compensated in 2 places.
Not truly symmetrical, but I like the cool look of that diamond
.Cheers,
Bob
If the circuit is working as intended, there should ideally be no voltage across the differential shunt resistor. If all of the Vbe are about the same, then the voltage across the current mirror degeneration resistors should be the same as the voltage across the VAS degeneration resistors. If there is little or no voltage across the shunt resistor, then reducing the value of the shunt resistor should not upset the needed values of the degeneration resistors.
Cheers,
Bob
Hi Mr. CordellHi Forr,
Neat circuit. Note that it is effectively a unipolar N-channel JFET input stage, what I like.
Also note it is really a four-stage amplifier; JFET LTP first stage, complementary "diamond" second stage, push-pull VAS third stage, Double EF output fourth stage.
Note also it is lag-lead compensated in 2 places.
Not truly symmetrical, but I like the cool look of that diamond
Cheers,
Bob
Like the post I responded about the article by Groner, this one has 3 stages. One extra stage will introduce one extra source of distortion. The second stage just turn the single end IPS to complementary output. But the idea is exactly the same as complementary IPS using single sided resistor loaded as output. I don't think this is better than the conventional symmetric IPS with resistor load even IF the added stage does not contribute any extra distortion.
Yes , neat circuit !!!
Kypton V is this circuit (below attachment).
Another similar one by vzaichenko ....
http://www.diyaudio.com/forums/soli...erformance-yet-rather-simple-hybrid-more.html
Here , the first stage is actually a VALVE. One of the only IPS's that can do this !
My "kypton' is more typical - Jfet or bjt first stage.
Nice amp - wonderful sound was reported (after I worked a few bugs out -
I had a lot of trouble with this amp ... and learned a lot , as well !).
PS - VERY hard to properly compensate ...
Making for real low THD20K ....
OS
Kypton V is this circuit (below attachment).
Another similar one by vzaichenko ....
http://www.diyaudio.com/forums/soli...erformance-yet-rather-simple-hybrid-more.html
Here , the first stage is actually a VALVE. One of the only IPS's that can do this !
My "kypton' is more typical - Jfet or bjt first stage.
Nice amp - wonderful sound was reported (after I worked a few bugs out -
I had a lot of trouble with this amp ... and learned a lot , as well !).
PS - VERY hard to properly compensate ...
Nope .... exact opposite , the 3rd stage gives quite the boost to 20K gain margin ...
Making for real low THD20K ....
OS
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Alan, you are mostly right.
But the single VAS's most evil fault isn't to do with slew. It's to do with overload recovery .. especially into LoZ loads.
Try simulating overload into 2R with Self's 4th Ed. fig 6.16
Upping the VAS current helps but the currents required become stupid very quickly.
The 'push-pull' VAS topologies are usually much better behaved. I rather like what Bob Cordell uses in his old MOSFET amp article.
________________________________
As for PSR, in http://www.diyaudio.com/forums/solid-state/235188-tpc-vs-tmc-vs-pure-cherry.html#post3474671, NPO/COG ceramics picked from the same batch for C1,3, easily take PSR below levels where layout is the dominant factor. Groner damns this with faint praise but in fact, this is a tried & tested production technique.
The circuit in that post could do with R13=68R to improve overload into 2R and there are versions with more sensible ULGF later in the thread with equivalent performance.
Improving PSRR
Hi Alan
Hi Alan
I don't see it either. It's overkill, the more so as you can improve the PSRR equally well with just one tiny cap, equal to Cdom. See C1 in:
Cheers, E.
30v/us ...lol.
-even the stupid leach does 125+.
This is what all the "excitement" about the CFA is about.
What I like about the CFA is the symmetry. Even a "stupid" (non-enhanced)
VAS gives symmetrical , non-sticking , slightly saturated overload characteristics.
The slew is just an added bonus at the expense of PSSR/offset (servo time).
PS - I'm used to 250V/us now - it really does add to the experience. And,
my CFA's typically only use 1 compensation cap - they are symmetrical (MIC).
VFA "leach" uses 2 .
OS
-even the stupid leach does 125+.
This is what all the "excitement" about the CFA is about.
What I like about the CFA is the symmetry. Even a "stupid" (non-enhanced)
VAS gives symmetrical , non-sticking , slightly saturated overload characteristics.
The slew is just an added bonus at the expense of PSSR/offset (servo time).
PS - I'm used to 250V/us now - it really does add to the experience. And,
my CFA's typically only use 1 compensation cap - they are symmetrical (MIC).
VFA "leach" uses 2
.OS
The point is you can make the asymmetrical VAS with CCS on one side to get the required slew rate to do the job. If 30V/uS is not enough, then increase current of the CCS to get higher slew rate. Also, use 3EF to lighten the capacitive load to the VAS.
Thanks
For overload recovery, you can still use diode to clamp the transistor to prevent it from going into forward forward bias. With EF as predriver to the VAS transistor, it is easy to clamp the transistor with a diode from the base of the EF to the collector of the VAS transistor to prevent it from sticking.
Good for sub duty ... overcompensated with a saturation clamp in case of
"party people "
. (thats my application) ...also , a great "test" input stage ... as being CCS based , quite independent of
rail voltages. I use the LIN to "fire up" my new output stages (test dawg)
PS - you don't say blame***@ on bob's thread - "dirty word" ....
OS
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Better just to use a topology that does not "stick" or saturate.
Lin is good for a educational tool (or sub duty) , but enhanced VAS symmetrical
designs rule the day for listening and durability.
OS
Hi Alan,
There is a shortcoming to using a diode calmp from VAS output to the input of the 2T VAS. That diode brings back into the picture the nonlinear capacitance that was neatly avoided by using the 2T VAS. Using an ordinary diode like the 1N4148 would make things much worse in this regard, since it has higher capacitance than the typical Ccb of a good VAS transistor.
Cheers,
Bob
Hi Forr,
Neat circuit. Note that it is effectively a unipolar N-channel JFET input stage, what I like.
Also note it is really a four-stage amplifier; JFET LTP first stage, complementary "diamond" second stage, push-pull VAS third stage, Double EF output fourth stage.
Note also it is lag-lead compensated in 2 places.
Not truly symmetrical, but I like the cool look of that diamond
Cheers,
Bob
Hi Bob,
Thanks for your comments.
The Sansui diamond circuit is US patended by Takahashi-Chickashige,
patent # 4,229,705, October 21, 1980.
It was used in some of Sansui preamps and amps.
Attached are the schematics of the AU-919 model with the detailed values for the frequency compensation.
For a slightly better quality, ask me them through an MP precising your email address.
Attachments
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Isn't that just because the p-p Vas can work in class AB so can deliver any current (within reason) you like, while the se Vas is limited to its standing current?
Jan
SE VAS is not limited to it's standing/bias current.
If you set bias to say 10mA in it's source/sink then when the VAS turns off the sink/source can't pull any more current than the bias setting value of 10mA.
But when the VAS turns on it can supply as much current as to blow it's self up.
We often see a current limiter set to at least two times bias current to prevent over current. That two times limits VAS output to +-bias current. i.e. +-10mApk
Setting the protection limiter to three times bias value allows +10mA and -20mA when full limiting is in action. That equals massive distortion, when Qprot has 600mVbe total VAS current is now sink = 10mA plus output demand of 20mApk = 30mApk
Reduce the peak output current demand to the bias value and the Qprot is now ~ 400mVbe i.e. is virtually off, (not conducting). Total VAS current is 10mA to sink/source and 10mApk to satisfy output demand = 20mApk
Omit the current limiter at your peril.
If you set bias to say 10mA in it's source/sink then when the VAS turns off the sink/source can't pull any more current than the bias setting value of 10mA.
But when the VAS turns on it can supply as much current as to blow it's self up.
We often see a current limiter set to at least two times bias current to prevent over current. That two times limits VAS output to +-bias current. i.e. +-10mApk
Setting the protection limiter to three times bias value allows +10mA and -20mA when full limiting is in action. That equals massive distortion, when Qprot has 600mVbe total VAS current is now sink = 10mA plus output demand of 20mApk = 30mApk
Reduce the peak output current demand to the bias value and the Qprot is now ~ 400mVbe i.e. is virtually off, (not conducting). Total VAS current is 10mA to sink/source and 10mApk to satisfy output demand = 20mApk
Omit the current limiter at your peril.
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