I've ordered a couple of the surface mount SOIC LM334Z ones and a handful of 0.1% resistors in 162R, 165R, 169R as I already have a couple of those little SOIC pinout adapter boards and CPC in the UK do free shipping.
LM334M - TEXAS INSTRUMENTS - CURRENT SOURCE, SMD, SOIC8, 334 | CPC
I don't think temps will get too high in my single deck install even with shunts, but it'd be good to work out what the values needed for a temperature independent source would be.
LM334M - TEXAS INSTRUMENTS - CURRENT SOURCE, SMD, SOIC8, 334 | CPC
I don't think temps will get too high in my single deck install even with shunts, but it'd be good to work out what the values needed for a temperature independent source would be.
it looks like the temp-indy config adds a diode (cancels tempco) and a resistor, which doesn't seem overly taxing. either may work just as well due to what seems to be a very favorable thermic regime.
I'm running some heavy duty shunts in my DDDAC1543 MKII (enough paralelled TDA1543s to matter) , and if situation is any similar I think provisions for thermic stability may provide better sleep, but may not be all that critical at the end of the day.
Whoever puts this together first may want to measure drift under some real world conditions and see if it's significant, and let us know.
Here it is guys! With many late nights..., 9Months son, bread&butter, and along with the unfriendly criticisms (crazy, idiots.., has more money than brain cells....). It was somewhat deflated. Nonetheless, I am now managed to complete this master piece of Doede's Engineering in association of Tent Labs years of experience in audio! Hopefully it sounds better then its look!
Wow Chan great job! I can't wait for Doede to Incorporate those shunts in the design.
I2S connection lengths?
Chanh,
Wouldn't it be better if the wire lengths from LR, Data, and BCK points on the main board to each DDDAC board be the same? Do unequal wire lengths create slight I2S timing issues and jitter?
Reducing the distances between VReg outputs to PCM1794 power consumption points and the distance between 47uf and film caps to their use points make a difference - and these distances are much smaller than stacked board wire length differences.
Any comments from the Forum experts?
Chanh,
Wouldn't it be better if the wire lengths from LR, Data, and BCK points on the main board to each DDDAC board be the same? Do unequal wire lengths create slight I2S timing issues and jitter?
Reducing the distances between VReg outputs to PCM1794 power consumption points and the distance between 47uf and film caps to their use points make a difference - and these distances are much smaller than stacked board wire length differences.
Any comments from the Forum experts?
my 2 cents... the conversion of digital sample into analog value happens during clock transition. meaning the other signals must be available at time of transition, this means that clock jitter causes the jitter issue. if for example the data line is longer or shorter does not change anything on the timing of the clock signal when it clocks the data signal. just check the datasheet for the timing diagrams, I think this tells it all.
now a sanity check. electricity travels with 3E8 m/s ergo, 1cm needs 33ps... the delays caused by propagation delays and parasitic capacitance are magnitudes higher, so for me the length is of no importance.
the point of proximity of supply has to do with parasitic inductance as far as I am concerned, not timing due to length of tracks
now a sanity check. electricity travels with 3E8 m/s ergo, 1cm needs 33ps... the delays caused by propagation delays and parasitic capacitance are magnitudes higher, so for me the length is of no importance.
the point of proximity of supply has to do with parasitic inductance as far as I am concerned, not timing due to length of tracks
There are audio digital clocks with a jitter of <= 1ps.
33ps/cm seems like a big number by comparison with 11cm for an 11 DDDAC stack representing a propagation delay of 363ps to the top board.
Am I comparing apples to apples here? I am way out of my expertise on this.
More thoughts on this subject. Each DDDAC board is converting I2S data into an analog signal in the audio band of 20-20k up to 80k. If each board in the stack is experiencing varying data/clock signal delays up to 363ps this difference is nothing compared to the highest audio band frequency and therefore is inaudible.
33ps/cm seems like a big number by comparison with 11cm for an 11 DDDAC stack representing a propagation delay of 363ps to the top board.
Am I comparing apples to apples here? I am way out of my expertise on this.
More thoughts on this subject. Each DDDAC board is converting I2S data into an analog signal in the audio band of 20-20k up to 80k. If each board in the stack is experiencing varying data/clock signal delays up to 363ps this difference is nothing compared to the highest audio band frequency and therefore is inaudible.
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I think you are mixing propagation delay, which is a constant and jitter which is a timing variable. the multiple decks actually are reducing jitter bottom line thanks to the averaging effect. did you read my comments on my website on my view on paralleling DACs and jitter effects? we did experiments with up to 240 DACs in parallel and still found improvement by increasing the number of DACs. the length of signal path was over a meter in difference in these set up.
Hi Carl,
I did the experiment with stock 11-Decks prior to mods, where I placed 6 decks on top and 5 below sandwiching the mainboard. I posted my setback findings here earlier. The result from this orientation was generating a kinda radio frequency interference, it sounded like some kind of radio out of tune. Despite filter caps upto 0.1uf were applied still not resolved! These findings aligned with previously reported here from another member where he has two on top and 2 below. To date I still ponder why?!? Always thought the lamination arrangement would have shorter i2s hence ideal but apparently not!
This part am not getting? Were you saying the distance between the 8V Shunt reg to DAC chip?
Cheers,
yes, it is best if a signal is applied to the DAC. if nothing is connected the internal clock features of the dac can run hot as it sees nothing to correlate with.
of course you could switch on spdif, than there is always signal if for whatever reason you do not want to connect the WaveIO to the DAC
of course you could switch on spdif, than there is always signal if for whatever reason you do not want to connect the WaveIO to the DAC
yea checked the rest of the e-301's i have
there all over the shop 250-340uA
the j502's were 400-440uA
the LM334Z/NOPB arrived took a 164r to set it, sounds very marginally better than the e-301 probably just begin a higher current and output bias
but took a while to settle in
i got the sioc version too ill try that next
CCS Board Test Results
My 2 transistor CCS circuit boards have over 100 hours of music play time and the DAC sounds amazing. I removed the CCS and reinserted the 6k resistor for comparison.
With the CCS the music has more dynamic energy and detail, a richer sounding midrange and bass. The music is more real and exciting. After putting back the 6k resistor the music sounded more compressed with less separation of voices and instruments, but it was still very pleasant sounding. The differences are small, but immediately noticeable. Once you experience the CCS sound you can't go back.
After a couple hours of playing the DAC with the 6k resistor I installed the simple adjustable JFET CCS circuit boards which have been cooking in a breadboard with a signal generator for 3 days. The excitement is back and the sq change did not seem small! Initial impression is that the simple JFET CCS might provide most if not all of the sound improvement of the 2 transistor CCS. I will let it play a couple of days to complete the break-in period and further report on the results.
The Rload voltage was 2.85 volts after installing the JFET boards. Rload resistance is 135 ohms. I adjusted the JFET CCS pot to bring them down to 2.75 volts. The voltage into pin 20 remained constant at 2.44volts and did not go down as I expected.
My 2 transistor CCS circuit boards have over 100 hours of music play time and the DAC sounds amazing. I removed the CCS and reinserted the 6k resistor for comparison.
With the CCS the music has more dynamic energy and detail, a richer sounding midrange and bass. The music is more real and exciting. After putting back the 6k resistor the music sounded more compressed with less separation of voices and instruments, but it was still very pleasant sounding. The differences are small, but immediately noticeable. Once you experience the CCS sound you can't go back.
After a couple hours of playing the DAC with the 6k resistor I installed the simple adjustable JFET CCS circuit boards which have been cooking in a breadboard with a signal generator for 3 days. The excitement is back and the sq change did not seem small! Initial impression is that the simple JFET CCS might provide most if not all of the sound improvement of the 2 transistor CCS. I will let it play a couple of days to complete the break-in period and further report on the results.
The Rload voltage was 2.85 volts after installing the JFET boards. Rload resistance is 135 ohms. I adjusted the JFET CCS pot to bring them down to 2.75 volts. The voltage into pin 20 remained constant at 2.44volts and did not go down as I expected.