F6 Amplifier

Could this be an implementation of US Pat. 4,107,619 (Fig.2)?
This patent [inventor Nelson Pass] taught STASIS {R} technology which was implemented in the power amps of Threshold Corp. I still have a Theshold S/150. At the time I bought it, it came with a complimentary copy of the granted patent. I 'll put Fig 2 in a pdf file in a following thread for the other DIYers to appreciate your point.
 
This patent [inventor Nelson Pass] taught STASIS {R} technology which was implemented in the power amps of Threshold Corp. I still have a Theshold S/150. At the time I bought it, it came with a complimentary copy of the granted patent. I 'll put Fig 2 in a pdf file in a following thread for the other DIYers to appreciate your point.
Please find attached Fig. 2 of US 4,107,619.
 

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F6 with P3 More Like in the F5

Connecting the potentiometer wiper this way is more like in the F5. Either way should work.
 

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What value gate resistors are you using?

Hi there ... 220 ohms .... I'm just doing some changes now, but seems to me that the issue is quite simply that applying the signal from the outputs to the gate for the TOP fet is probably not a good idea - that fet is in a non inverting config so what I'm doing is applying positive feedback instead of negative feedback (for the top half ) almost ensuring that I get oscillations coming in at some point. I venture.

Bottom half is inverting , so issue doesn't crop up there.

Anyway, reconfiging the biasing with a bypass cap for the top half and taking bias ground from zero volts Instead of output to see if it works as I think it should.

Trying to learn at least through my own mistakes ......
 

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wow .. fabulous appetizer while we await the main course - nicely done and phenomenal results !

Would love to hear how any breadboarded results go - I have a nice start but my setup seems to oscillate now at the drop of a hat - fried two more latfets :( ... no clue why because the same setup with complementary outputs was very well behaved....




Please clarify the conditions of your test. Were the secondaries of the transformer driving the latfets in-phase according to the simplified F6 schematic? There are a total of four key experiments for a multiway comparison of amplifiers' performance.
  • N [or P] channel output FETs driven in phase and out of phase
  • Complementary N and P channel output FETs driven in phase and out of phase
Those of you lucky DIYers who have the capabilty to simulate, please do so. You will then generate a comprehensive review which is worthwhile [and welcome] to publish as an article in diyAudio?
 
Please clarify the conditions of your test

. Were the secondaries of the transformer driving the latfets in-phase according to the simplified F6 schematic?
>>out of phase<<

  • N [or P] channel output FETs driven in phase and out of phase
    >>N channel, out of phase.<<
  • Complementary N and P channel output FETs driven in phase and out of phase
    >>in phase, if out of phase all you see is the residual distortion coming from mismatches, ie no signal at the output<<
 
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What am I saying! You and I cannot draw a schematic like the simplified F6 using complementary devices [per the earlier comment of kasey197; please clarify]; be it bjt or MOSFET. But I can do so with enhancement [top] and depletion [bottom] N-channel JFETs.

I'm not getting it

both types - depletion and enhancement - are "opening" more with rising voltage on gate (ref. source)
difference is just in biasing voltage - one needs negative , other needs positive (ref.source)

so - if you are going to modulate them in same phase , nothing will happen on output node , considering voltage potential vs. gnd

only difference will reflect difference in their xconductance/gain

as I said several times - I'm digging Pa's schm from post #1 only in case that modulation of upper output Jfet is decreased in deliberate amount , having final effect as something opposite of Mu output stage characteristic (Um , maybe :clown: )

anyway - if we are trying to anticipate Pa's logic here , we are on thin ice

it's better to save fingertips and breath and few leftover brain cells we have .... except in case some of us are willing to make something just based on concept ........

unfortunately - I'm not having lately either time or energy or back to try even some things already drawn ; so - this time I'll pass practical anticipation check , probably thinking do I have something enough valuable to sell and to buy cheapest AP station

:rofl:
 
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Please clarify the conditions of your test

>>in phase, if out of phase all you see is the residual distortion coming from mismatches, ie no signal at the output<<
I am confused by your answer. Out of phase drive with similar polarity devices must produce an output signal; e.g. for the schematic in post #38 which was a common [maybe commercial] power amplifier.

But; you have stumbled on a test to match devices dynamically! Maybe the lowest output distortion means a very good to excellent match.
 
To clarify: for the complementary push pull output stage with n and p channel fets: signal applied in phase.

For the test I did here, using same polarity fets (n channel) and biased like is described above, signal is applied out of phase. The sim results shown above also use out of phase.