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Design Rule Verification Report

Date : 13/05/2012
Time : 6:45:05 PM
Elapsed Time : 00:00:02
Filename : C:\Phil\Electronics\CAD\Dig_Cross_2011\EXPORT_2012_04\Dig_Cross_V32\Digital_Crossover_v32\Documents\DAC_Board.PcbDoc
Warnings : 0
Rule Violations : 9

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=12mil) ((IsRegion)),(All) 0
Room Output Filters - Differential-1 (Bounding Region = (3615mil, 1045mil, 5505mil, 4180mil) (InComponentClass('Output Filters - Differential-1')) 0
Net Antennae (Tolerance=0mil) (All) 0
Minimum Solder Mask Sliver (Gap=5mil) (All),(All) 9
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=14mil) (Max=255mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Width Constraint (Min=10mil) (Max=255mil) (Preferred=10mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=15mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 9


Minimum Solder Mask Sliver (Gap=5mil) (All),(All)
Via (4770mil,1320mil) Top Layer to Bottom Layer Pad P1-20(4770mil,1240mil) Multi-Layer
Via (4370mil,1310mil) Top Layer to Bottom Layer Pad P1-12(4370mil,1240mil) Multi-Layer
Pad R37-1(4860mil,2790mil) Multi-Layer Pad R33-2(4850mil,2700mil) Multi-Layer
Pad C59-1(4860mil,3160mil) Multi-Layer Pad R41-1(4770mil,3160mil) Multi-Layer
Via (4680mil,1540mil) Top Layer to Bottom Layer Pad C46-2(4630mil,1590mil) Top Layer
Via (4135mil,1875mil) Top Layer to Bottom Layer Pad C47-1(4190mil,1920mil) Top Layer
Via (4135mil,1875mil) Top Layer to Bottom Layer Pad R32-1(4080mil,1920mil) Top Layer
Via (3920mil,1545mil) Top Layer to Bottom Layer Pad R53-1(3975mil,1590mil) Top Layer
Via (3920mil,1545mil) Top Layer to Bottom Layer Pad R54-1(3865mil,1590mil) Top Layer
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